ICS9150F-04 查看數據表（PDF） - Integrated Circuit Systems
零件编号
产品描述 (功能)
生产厂家
ICS9150F-04 Datasheet PDF : 19 Pages
| |||
ICS9150- 04
General I2C serial interface information
A. For the clock generator to be addressed by an I2C controller, the following address must be sent as a start sequence,
with an acknowledge bit between each byte.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
Then Byte 0, 1, 2, etc in
sequence until STOP.
D2(H)
B.
The clock generator is a slave/receiver I2C component. It can "read back "(in Philips I2C protocol) the data stored in the
latches for verification. (set R/W# to 1 above). There is no BYTE count supported, so it does not meet the Intel SMB
PIIX4 protocol.
Clock Generator
Address (7 bits)
A(6:0) & R/W#
D3(H)
ACK
Byte 0
ACK
Byte 1
ACK Byte 0, 1, 2, etc in sequence until STOP.
C. The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D. The input is operating at 3.3V logic levels.
E. The data byte format is 8 bit bytes.
F.
To simplify the clock generator I2C interface, the protocol is set to use only block writes from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has
been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two
bytes. The data is loaded until a Stop sequence is issued.
G.
The Fixed clocks 24, 48MHz are not addressable in the registers for Stopping. These outputs are always running, except
in Tristate Mode.
H. At power-on, all registers are set to a default condition. See Byte 0 detail for default condition, Bytes 1 through 5 default
to a 1 (Enabled output state)
Serial Configuration Command Bitmap
Byte0: Functionality and Frequency Select Register (default bits 0-3 to logic 0)
Bit
Bit 7
Bit 6:4
Bit 3
Bit 2
Bit 1
Bit 0
Description
0 - ±1.5% Spread Spectrum Modulation
1 - ±0.5% Spread Spectrum Modulation
Bit6 Bit5 Bit4
111
110
101
100
011
010
001
000
CPU clock
66.8
60.0
75.0
83.3
68.5
83.3
75.0
50.0
PCI
33.4(1/2 CPU)
30.0 (1/2 CPU)
37.5 (1/2 CPU)
33.3
34.5 (1/2 CPU)
41.65 (1/2 CPU)
32.0
25.0 (1/2 CPU)
0 - Frequency is selected by hardware select, Latched
Inputs
1 - Frequency is selected by Bit 6:4 (above)
0 - Spread Spectrum center spread type. (default)
1 - Spread Spectrum down spread type.
Bit1 Bit0
1 1 - Tri-State
1 0 - Spread Spectrum Enable
0 1 - Testmode
0 0 - Normal Operation
PWD
0
Note 1
Note 1. Default at Power-up will be for
latched logic inputs to define the
frequency. Bits 4, 5, 6 are default
to 000. If bit 3 is written to a 1 to
use Bits 6:4, then these should be
defined to the desired frequency at
same write cycle.
Note: PWD = Power-Up Default
0
0
0
0
I2C is a trademark of Philips Corporation
6
Share Link: 