ML4818 查看數據表（PDF） - Fairchild Semiconductor
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ML4818 Datasheet PDF : 13 Pages
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ML4818
Pin Configuration
24-Pin Power DIP (P24)
GND
CT
RAMP
ILIM
E/A OUT
GND
GND
INV
SOFT START
SHUTDOWN
RT
RCRESET
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
TOP VIEW
VREF
GND
B1 OUT
B2 OUT
VCC
GND
GND
A1 OUT
A2 OUT
GND
RDELAY
CLOCK
PRODUCT SPECIFICATION
Pin Description
Pin
1
2
3
4
5
6,7
8
9
10
11
12
13
14
15
16
17
18,19
20
21
22
23
24
Name
GND
CT
RAMP
ILIM
E/A OUT
GND
INV
SOFT START
SHUTDOWN
RT
RCRESET
CLOCK
RDELAY
GND
A2 OUT
A1 OUT
GND
VCC
B2 OUT
B1 OUT
GND
VREF
Function
Ground
Timing capacitor for oscillator
Non-inverting input to main comparator. Connected to current sense resistor for
current mode
Current limit sense pin. Normally connected to current sense resistor
Output of error amplifier and input to PWM comparator
Ground and substrate
Inverting input to error amp
Normally connected to soft start capacitor
Pulling this pin low puts the IC into a power down mode and turns off all outputs.
This pin is internally pulled up to VREF.
Resistor which sets discharge current for oscillator timing capacitor
Timing elements for Integrating fault detection and reset delay circuits
Oscillator output
Resistor to ground on this pin programs the amount of delay from the time an
output turns off until its complementary output turns on
Ground
High current totem pole output A1
High current totem pole output A2
Ground and substrate
Positive supply for the IC
High current totem pole output B1
High current totem pole output B2
Ground
Buffered output for the 5V voltage reference
2
REV. 1.0.3 6/21/01
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