IN74HC4046AD 查看數據表（PDF） - Integral Corp.

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IN74HC4046AD

PHASE-LOCKED LOOP

Integral Corp. 

IN74HC4046A

Figure 6. Logic Diagram for Phase Comparators

Phase Comparator 1

VCO input must be VCC and the phase detector

This comparator is a simple XOR gate

inputs must be 180 degrees out of phase.

similar to the IN74HC86. Its operation is similar to

The XOR is more susceptible to locking onto

an overdriven balanced modulator. To maximize

harmonics of the SIGIN than the digital phase

lock range the input frequencies must have a 50%

detector 2. For instance, a signal 2 times the VCO

duty cycle. Typical input and output waveforms

frequency results in the same output duty cycle as

are shown in Figure 7. The output of the phase

a signal equal to the VCO frequency. The

detector feeds the loop filter which averages the

difference is that the output frequency of the 2f

output voltage. The frequency range upon which

example is twice that of the other example. The

the PLL will lock onto if initially out of lock is

loop filter and VCO range should be designed to

defined as the capture range.The capture range

prevent locking on to harmonics.

for phase detector 1 is dependent on the loop

Phase Comparator 2

filter design. The capture range can be as large

This detector is a digital memory network. It

as the lock range, which is equal to the VCO

consists of four flip-flops and some gating logic, a

frequency range.

three state output and a phase pulse output as

To see how the detector operates, refer to

shown in Figure 6. This comparator acts only on

Figure 7. When two square wave signals are

the positive edges of the input signals and is

applied to this comparator, an output waveform

independent of duty cycle.

(whose duty cycle is dependent on the phase

Phase comparator 2 operates in such a

difference between the two signals) results. As

way as to force the PLL into lock with 0 phase

the phase difference increases, the output duty

difference between the VCO output and the signal

cycle increases and the voltage after the loop filter

input positive waveform edges. Figure 8 shows

increases. In order to achieve lock when the PLL

some typical loop waveforms. First assume that

input frequency increases, the VCO input voltage

SIGIN is leading the COMPIN. This means that the

must increase and the phase difference between

VCO’s frequency must be increased to bring its

COMPIN and SIGIN will increase. At an input

leding edge into proper phase alignment. Thus

frequency equal to fmin, the VCO input is at 0 V

the phase detector 2 output is set high. This will

cause the loop filter to charge up the VCO input,

increasing the VCO frequency. Once the leading

edge of the COMPIN is detected, the output goes

TRI-STATE holding the VCO input at the loop

filter voltage. If the VCO still lags the SIGIN then

the phase detector will again charge up the VCO

input for the time between the leading edges of

both waveforms.

Figure 7. Typical Waveforms for PLL Using

Phase Comparator 1

This requires the phase detector output to

be grounded; hence, the two input signals must

be in phase. When the input frequency is fmax, the

If the VCO leads the SIGIN then when the

leading edge of the VCO is seen; the output of the

phase comparator goes low. This discharges the

loop filter until the leading edge of the SIGIN is

detected at which time the output disables itself

8

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