AD7243 查看數據表（PDF） - Analog Devices

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AD7243

LC2MOS 12-Bit Serial DACPORT

Analog Devices 

AD7243

TERMINOLOGY (Continued)

This “knee” is an offset effect, not a linearity error, and the

transfer function would have followed the dotted line if the out-

put voltage could have gone negative.

Normally, linearity is measured between zero (all 0s input code)

and full scale (all 1s input code) after offset and full scale have

been adjusted out or allowed for, but this is not possible in

single supply operation if the offset is negative, due to the knee

in the transfer function. Instead, linearity of the AD7243 in the

unipolar mode is measured between full scale and the lowest

code which is guaranteed to produce a positive output voltage.

This code is calculated from the maximum specification for

negative offset. For the A and B versions the linearity is mea-

sured between Codes 3 and 4095. For the S grade, linearity is

measured between Code 5 and Code 4095.

Differential Nonlinearity

Differential Nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of ± 1 LSB or less

over the operating temperature range ensures monotonicity.

Unipolar Offset Error

Unipolar Offset Error is the measured output voltage from

VOUT with all zeros loaded into the DAC latch when the DAC is

configured for unipolar output. It is due to a combination of the

offset errors in the DAC and output amplifier.

PIN CONFIGURATION

DIP and SOIC

REFIN 1

REFOUT 2

CLR 3

BIN/COMP 4

SCLK 5

SDIN 6

SYNC 7

DGND 8

AD7243

16 VDD

15 VSS

14 VOUT

TOP VIEW

(Not to Scale)

13 ROFS

12 AGND

11 SDO

10 DCEN

9 LDAC

CIRCUIT INFORMATION

D/A Section

The AD7243 contains a 12-bit voltage mode D/A converter

consisting of highly stable thin film resistors and high speed

NMOS single-pole, double-throw switches. The output voltage

from the converter has the same polarity as the reference volt-

age, REFIN, allowing single supply operation.

2R

2R

R OFS

R

R

R

R

R

VOUT

2R

2R

2R

DB0 DB1

2R

DB9

2R

DB10

2R

DB11

REFIN*

AGND

*BUFFERED REFIN VOLTAGE

SHOWN FOR ALL 1S

ON DAC

Figure 2. D/A Simplified Circuit Diagram

Internal Reference

The AD7243 has an on-chip temperature compensated buried

Zener reference which is factory trimmed to 5 V ± 50 mV. The

reference voltage is provided at the REFOUT pin. This refer-

ence can be used to provide the reference voltage for the D/A

converter (by connecting the REFOUT pin to the REFIN pin.)

The reference voltage can also be used as a reference for other

components and is capable of providing up to 500 µA to an ex-

ternal load. The maximum recommended capacitance on

REFOUT for normal operation is 50 pF. If the reference is re-

quired for external use with capacitive loads greater than 50 pF

then it should be decoupled to AGND with a 200 Ω resistor in

series with a parallel combination of a 10 µF tantalum capacitor

and a 0.1 µF ceramic capacitor.

REFOUT

200⍀

10␮F

0.1␮F

EXT

LOAD

Figure 3. Reference Decoupling Scheme

External Reference

In some applications, the user may require a system reference or

some other external reference to drive the AD7243. References

such as the AD586 provide an ideal external reference source

(see Figure 10). The REFIN voltage is internally buffered by a

unity gain amplifier before being applied to the D/A converter.

The D/A converter is scaled for a 5 V reference and the device is

tested with 5 V applied to REFIN. Other reference voltages may

be used with degraded performance. Figure 4 shows the typical

degradation in linearity vs. REFIN.

1.0

0.9

VDD = +15V

VSS = –15V

0.8

TA = +25؇C

0.7

0.6

0.5

0.4

INL

0.3

0.2

DNL

0.1

0.0

2

3

4

5

6

7

REFIN – Volts

8

9

Figure 4. Typical Linearity vs. REFIN Voltage

Op Amp Section

The output of the voltage mode D/A converter is buffered by a

noninverting CMOS amplifier. The ROFS input allows three out-

put voltage ranges to be selected. The buffer amplifier is capable

of developing +10 V across a 2 kΩ load to AGND.

The output amplifier can be operated from a single +12 V to

+15 V supply by tying VSS = 0 V.

The amplifier can also be operated from dual supplies to allow

an additional bipolar output range of –5 V to +5 V. Dual supplies are

necessary for the bipolar output range but can also be used for

the unipolar ranges to give faster settling time to voltages near

REV. A

–5–

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