SPT7937SIR 查看數據表（PDF） - Signal Processing Technologies
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SPT7937SIR Datasheet PDF : 11 Pages
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ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AVDD ......................................................................... +6 V
DVDD ......................................................................... +6 V
OVDD ......................................................................... +6 V
Input Voltages
Analog Input .................................... –0.7 V to VDD +0.7 V
CLK Input ................................................................... VDD
AVDD – DVDD ...................................................... ±100 mV
AGND – DGND .................................................. ±100 mV
Output
Digital Outputs ....................................................... 10 mA
Temperature
Operating Temperature ............................. –40 to +85 °C
Junction Temperature ......................................... +175 °C
Lead Temperature, (soldering 10 seconds) ........ +300 °C
Storage Temperature ............................... –65 to +150 °C
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, VDD=+5.0 V, ƒS=28 MSPS, VIN=0 to 4 V, VRHS=4.0 V, VRLS=0.0 V, unless otherwise specified.
PARAMETERS
TEST
CONDITIONS
TEST
LEVEL
SPT7937
MIN
TYP
MAX
Resolution
12
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
V
±1.75
V
±0.9
VI
Guaranteed
Analog Input
Input Voltage Range
Input Capacitance
Input Bandwidth
Input Impedance
–Full-Scale Error1
+Full-Scale Error1
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time (TAP)
Aperture Jitter Time
Clock Duty Cycle
Over-Voltage Recovery Time2
Dynamic Performance
Effective Number of Bits
ƒIN = 3.58 MHz
ƒIN = 10 MHz
Reference Input
Resistance
Voltage Range3
VRHS
VRLS
VRHS – VRLS
VI
VRLS
V
5.0
V
250
35
V
1.0
V
0.12
VI
28
V
1
IV
V
1.0
V
5.0
V
40
V
10.3
VI
10.0
VI
350
500
IV
3.0
IV
0.0
V
1.0
4.0
VRHS
14
60
36
650
VDD
2.0
5.0
UNITS
Bits
LSB
LSB
V
pF
MHz
kΩ
LSB
%FS
MHz
MHz
Clock Cycles
ns
ps (RMS)
%
ns
Bits
Bits
Ω
V
V
V
1 The full-scale range spans the reference ladder sense pins, VRHS and VRLS. Refer to the Voltage Reference section for discussion.
2 Due to internal architecture, over-voltage recovery time is less than one clock cycle (i.e., 25 ns at ƒCLK = 40 MHz).
3 For optimum performance, the full-scale voltage range (VRHS–VRLS) should be between 3 V to 5 V.
SPT
2
SPT7937
1/14/00
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