SPT7912SCJ 查看數據表（PDF） - Signal Processing Technologies
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SPT7912SCJ Datasheet PDF : 11 Pages
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The maximum scaling factor for device operation is ± 20% of
the recommended reference voltages of VFT and VFB. How-
ever, because the device is laser trimmed to optimize perfor-
mance with VSB and VST equal to -2.0 V and +2.0 V respec-
tively, the accuracy of the device will degrade if operated
beyond a ± 2% range.
The following errors are defined:
+FS error = top of ladder offset voltage = ∆(+FS -VST)
-FS error = bottom of ladder offset voltage = ∆(-FS -VSB)
Where the +FS (full scale) input voltage is defined as the input
approximately 1 LSB above the output transition of 1—10
and 1—11 and the -FS input voltage is defined as the input
approximately 1 LSB below the output transition of 0—00 and
0—01.
An example of a reference driver circuit recommended is
shown in figure 2. IC1 is REF-03, the +2.5 V reference with a
tolerance of 0.6% or ± 0.015 V. The potentiometer R1 is
10 kΩ and supports a minimum adjustable range of up to
150 mV. IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1% with good
TC tracking to maintain a 0.3 LSB matching between VFT and
VFB. If 0.1% matching is not met, then potentiometer R4 can
be used to adjust the VFB voltage to the desired level. R1 and
R4 should be adjusted such that VST and VSB are exactly
+2.0 V and -2.0 V respectively.
ANALOG INPUT
VIN1 and VIN2 are the analog inputs. Both inputs are tied to
the same point internally. Either one may be used as an
analog input sense and the other for an input force. The inputs
can also be tied together and driven from the same source.
The full scale input range will be 80% of the reference voltage
or ±2 volts with VFB=-2.5 V and VFT=+2.5 V.
The drive requirements for the analog inputs are minimal
when compared to conventional Flash converters due the
SPT7912’s extremely low input capacitance of only 5 pF and
very high input impedance of 300 kΩ. For example, for an
input signal of ± 2 V p-p with an input frequency of 10 MHz,
the peak output current required for the driving circuit is only
628 µA.
CLOCK INPUT
The clock inputs (CLK, CLK ) are designed to be driven
differentially with ECL levels. Differential clock driving is
highly recommended to minimize the effects of clock jitter.
The clock may be driven single ended since CLK is inter-
nally biased to -1.3 V. CLK may be left open, but a .01 µF
bypass capacitor to AGND is recommended. As with all high
speed circuits, proper terminations are required to avoid
signal reflections and possible ringing that can cause the
device to trigger at an unwanted time.
The clock input duty cycle should be 50% where possible, but
performance will not be degraded if kept within the range of
40-60%. However, in any case the clock pulse width (tpwH)
must be kept at 300 ns maximum to ensure proper operation
of the internal track and hold amplifier (see timing diagram).
The analog input signal is latched on the rising edge of the CLK.
DIGITAL OUTPUTS
The format of the output data (D0-D11) is straight binary.
(See table II.) These outputs are ECL 10K and 10KH
compatible with the output circuit shown in figure 3. The
outputs are latched on the rising edge of CLK with a propa-
gation delay of 5 ns. There is a one clock cycle latency
between CLK and the valid output data (see timing diagram).
These digital outputs can drive 50 ohms to ECL levels when
pulled down to -2 V. Output loading pulled down to -5.2 V is
not recommended. The total specified power dissipation of
the device does not include the power used by these loads.
The additional power used by these loads can vary between
10 and 300 mW typically (including the overrange load)
depending on the output codes. If lower power levels are
desired, the output loads can be reduced, but careful consid-
eration to the resistive and capacitive loads in relation to the
operating frequency must be considered.
Table II - Output Data Information
ANALOG INPUT
>+2.0 V + 1/2 LSB
+2.0 V -1 LSB
0.0 V
-2.0 V +1 LSB
<-2.0 V
OVERRANGE
D12
OUTPUT CODE
D11-DO
1
1111 1111 1111
O
1111 1111 111Ø
O
ØØØØ ØØØØ ØØØØ
O
OOOO OOOO OOOØ
O
OOOO OOOO OOOO
(Ø indicates the flickering bit between logic 0 and 1).
SPT
8
SPT7912
3/10/97
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