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HIP1015

Power Distribution Controllers

Intersil 

HIP1015,HIP1016

HIP1015, HIP1016 Description and Operation

The HIP1015 and HIP1016 are single power supply

distribution controllers for generic hot swap applications. The

HIP1015 is targeted for +12V switching applications

whereas the HIP1016 is targeted for +5V applications as

each has an undervoltage (UV) threshold level ~17% lower

than the nominal +12V and +5V, respectively.

The HIP1015 and HIP1016 features include a highly

accurate programmable Overcurrent (OC) detecting

comparator, programmable current limiting regulation with

programmable time delay to latch off and programmable soft

start turn-on ramp all set with a minimum of external passive

components. The HIP1015 and HIP1016 also include severe

overcurrent protection that immediately shuts down the

MOSFET switch should the load current cause the OC

voltage threshold to exceed the programmed OC level by

150mV. Additionally the HIP1015 and HIP1016 have an UV

indicator and an OC latch indicator.

Upon initial power up, the HIP1015 or HIP1016 can either

isolate the voltage supply from the load by holding the external

N-Channel MOSFET switch off or apply the supply rail voltage

directly to the load for true hot swap capability. In either case

the HIP1015 and HIP1016 turns on in a soft start mode

protecting the supply rail from sudden in-rush current. The

PWRON pin must be pulled low for the device to isolate the

power supply from the load by holding the external N-channel

MOSFET off, otherwise with the PWRON pin held high or

floating the HIP1015 and HIP1016 will be in true hot swap

mode.

At turn-on, the gate capacitor of the external N-Channel

MOSFET is charged with a 10µA current source resulting in

a programmable ramp (soft start turn-on). The internal

HIP1015 charge pump supplies the gate drive for the 12V

supply switch driving that gate to VDD +5V. The HIP1016

gate drive is limited to the chip bias voltage.

Load current passes through the external current sense

resistor. When the voltage across the sense resistor

exceeds the user programmed Overcurrent voltage

threshold value, (See Table 1 for RISET programming

resistor value and resulting nominal overcurrent threshold

voltage, VOC) the controller enters current regulation. At this

time, the time-out capacitor, on CTIM pin starts charging with

a 20mA current source and the controller enters the current

limit time to latch-off period. The length of the current limit

time to latch-off period is set by the single external capacitor

(See Table 2 for CTIM capacitor value and resulting nominal

current limited time out to latch-off period.) placed from the

CTIM pin (pin 6) to ground. The programmed current level is

held until either the OC event passes or the time out period

expires. If the former is the case then the N-Channel

MOSFET is fully enhanced and the CTIM capacitor is

discharged. Once CTIM charges to 1.87V, signaling that the

time out period has expired an internal latch is set whereby

the FET gate is quickly pulled to 0V turning off the N-

Channel MOSFET switch, isolating the faulty load.

TABLE 1.

RISET RESISTOR

10kΩ

4.99kΩ

NOMINAL OC VTH

200mV

100mV

2.5kΩ

50mV

750Ω

NOTE: Nominal Vth = RISET x 20µA.

15mV

TABLE 2.

CTIM CAPACITOR NOMINAL CURRENT LIMITED PERIOD

0.022µF

2ms

0.047µF

4.4ms

0.1µF

9.3ms

NOTE: Nominal time-out period in seconds = CTIM x 93kΩ.

The HIP1015 and HIP1016 respond to a severe overcurrent

load (defined as a voltage across the sense resistor >150mV

over the OC Vth set point) by immediately, driving the N-

Channel MOSFET gate to 0V in less than 1µs. The gate

voltage is then slowly ramped up turning on the N-Channel

MOSFET to the programmed current limit level, this is the

start of the time out period.

Upon an UV condition the PGOOD signal will pull low when

tied high through a resistor to the logic supply. This pin is an

UV fault indicator. For an OC latch off indication, monitor

CTIM, pin 6. This pin will rise rapidly from 1.9V to 12V once

the time out period expires.

The HIP1015 and HIP1016 are reset after an OC latch-off

condition by a low level on the PWRON pin and is turned on

by the PWRON pin being driven high.

Application Considerations

During the Time-Out Delay Period with the HIP1015 and

HIP1016 in current limit mode, the VGS of the external N-

Channel MOSFETs is reduced driving the N-Channel

MOSFET switch into a high rDS(ON) state. Thus avoid

extended time out periods as the external N-Channel

MOSFETs may be damaged or destroyed due to excessive

internal power dissipation. Refer to the MOSFET

manufacturers data sheet for SOA information.

With the high levels of inrush current e.g., highly capacitive

loads and motor start up currents, choosing the current

limiting level is crucial to provide both protection and still

allow for this inrush current without latching off. Consider this

in addition to the time out delay when choosing MOSFETs

for your design.

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