ML4812 查看數據表（PDF） - Fairchild Semiconductor

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ML4812

Power Factor Controller

Fairchild Semiconductor 

ML4812

TYPICAL APPLICATIONS (Continued)

Choose 4.75kΩ, 1%. One more critical component in the

voltage regulation loop is the feedback capacitor for the

error amplifier. The voltage loop bandwidth should be set

such that it rejects the 120Hz ripple which is present at

the output. If this ripple is not adequately attenuated it

will cause distortion on the input current waveform.

Typical bandwidths range anywhere from a few Hertz to

15Hz. The main compromise is between transient

response and distortion. The feedback capacitor can be

calculated using the following formula:

CF

=

1

3.142 ´ R1

´

BW

CF

=

3.142 ´

1

356kΩ

´

2Hz

=

0.44mF

(19)

OVERVOLTAGE PROTECTION (OVP) COMPONENTS

The OVP loop should be set so that there is no interaction

with the voltage control loop. Typically it should be set to

a level where the power components are safe to operate.

Ten to fifteen volts above VOUT is generally a good

setpoint. This sets the maximum transient output voltage

to about 395V. By choosing the high voltage side resistor

of the OVP circuit the same way as above i.e. R4 = 356K

then R5 can be calculated as:

R5

=

VREF ´ R 4

VOVP - VREF

=

5V ´ 356kΩ

395V - 5V

=

4.564kΩ

(20)

Choose 4.53kΩ, 1%. Note that R1, R2, R4 and R5 should

be tight tolerance resistors such as 1% or better.

CONTROLLER SHUTDOWN

The ML4812 provides a shutdown pin which could be

used to shutdown the IC. Care should be taken when this

pin is used because power supply sequencing problems

could arise if another regulator with its own bootstrapping

follows the ML4812. In such a case a special circuit

should be used to allow for orderly start up. One way to

accomplish this is by using the reference voltage of the

ML4812 to inhibit the other controller IC or to shut down

its bias supply current.

OFF-LINE START-UP AND BIAS SUPPLY GENERATION

The ML4812 can be started using a “bleed resistor” from

the high voltage bus. After the voltage on VCC exceeds

16V, the IC starts up. The energy stored on the 330µF,

C15, capacitor supplies the IC with running power until

the supplemental winding on L1 can provide the power to

sustain operation.

The values of the start-up resistor R10 and capacitor C15

may need to be optimized depending on the application.

The charging waveform for the secondary winding of L1 is

an inverted chopped sinusoid which reaches its peak

when the line voltage is at its minimum. In this example,

C9 = 0.1µF, C15 = 330µF, D8 = 1N4148, R10 = 39kΩ,

2W.

ENHANCEMENT CIRCUIT

The power factor enhancement circuit shown in Figure 12

is described in detail in Application Note 11. It improves

the power factor and lowers the input current harmonics.

Note that the circuit meets IEC 1000-3-2 specifications

(with the enhancement) on the harmonics by a large

margin while correcting the input power factor to better

than 0.99 under most steady state operating conditions.

CONSTRUCTION AND LAYOUT TIPS

High frequency power circuits require special care during

breadboard construction and layout. Double sided printed

circuit boards with ground plane on one side are highly

recommended. All critical switching leads (power FET,

output diode, IC output and ground leads, bypass

capacitors) should be kept as small as possible. This is to

minimize both the transmission and pick-up of switching

noise.

There are two kinds of noise coupling; inductive and

capacitive. As the name implies inductive coupling is due

to fast changing (high di/dt) circulating switching currents.

The main source is the loop formed by Q1, D5, and

C3–C4. Therefore this loop should be as small as possible,

and the above capacitors should be good high frequency

types.

The second form of noise coupling is due to fast changing

voltages (high dv/dt). The main source in this case is the

drain of the power FET. The radiated noise in this case can

be minimized by insulating the drain of the FET from the

heatsink and then tying the heatsink to the source of the

FET with a high frequency capacitor (CH in Figure 12).

The IC has two ground pins named PWR GND and Signal

GND. These two pins should be connected together with

a very short lead at the printed circuit board exit point. In

general grounding is very important and ground loops

should be avoided. Star grounding or ground plane

techniques are preferred.

10

REV. 1.0 10/10/2000

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