ML4812CQ 查看數據表（PDF） - Fairchild Semiconductor
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ML4812CQ Datasheet PDF : 16 Pages
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ML4812
PIN CONFIGURATION
ML4812
16-Pin PDIP (P16)
ISENSE 1
GM OUT 2
16 CT
15 GND
EA OUT 3
EA– 4
OVP 5
14 VREF
13 VCC
12 OUT
ISINE 6
RAMP COMP 7
11 PWR GND
10 SHDN
RT 8
9 CLOCK
TOP VIEW
ML4812
20-Pin PLCC (Q20)
EA OUT
EA–
NC
OVP
ISINE
3 2 1 20 19
4
18 VREF
5
17 VCC
6
16 NC
7
15 OUT
8
14 PWR GND
9 10 11 12 13
TOP VIEW
PIN DESCRIPTION
PIN NAME
FUNCTION
1
ISENSE
Input from the current sense
transformer to the non-inverting input
of the PWM comparator.
2 GM OUT Output of gain modulator.
A resistor to ground on this pin
converts the current to a voltage.
This pin is clamped to 5V and tied
to the inverting input of the PWM
comparator.
3 EA OUT Output of error amplifier.
4 EA–
Inverting input to error amplifier.
5 OVP
Input to over voltage comparator.
6
ISINE
7 RAMP
COMP
Current gain modulator input.
Buffered output from the oscillator
ramp (CT). A resistor to ground sets the
current which is internally subtracted
from the product of ISINE and IEA in
the gain modulator.
PIN NAME
FUNCTION
8 RT
9 CLOCK
10 SHDN
Oscillator timing resistor pin. A 5V
source sets a current in the external
resistor which is mirrored to charge
CT.
Digital clock output.
A TTL compatible low level on this pin
turns off the output.
11 PWR GND Return for the high current totem pole
output.
12 OUT
High current totem pole output.
13 VCC
14 VREF
Positive Supply for the IC.
Buffered output for the 5V voltage
reference.
15 GND
Analog signal ground.
16 CT
Timing capacitor for the oscillator.
2
REV. 1.0 10/10/2000
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