XWM8148CFT/V 查看數據表（PDF） - Wolfson Microelectronics plc
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XWM8148CFT/V Datasheet PDF : 43 Pages
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WM8148
OUTPUT DATA
Production Data
OEB
OP[11:0]
tPZE
Hi-Z
tPEZ
Hi-Z
Figure 5 Output Data Enable Timing
MCLK
FDEL[1:0] = 01 OP[11:0]
FDEL[1:0] = 00 OP[11:0]
DEFAULT
FDEL[1:0] = 10 OP[11:0]
tPD
tPD
FDEL[1:0] = 11 OP[11:0]
Figure 6 Output Data Timing (Including Fine Latency Control By FDEL[1:0])
tPD
tPD
TEST CONDITIONS
AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 48MHz unless
otherwise stated (AVDD denotes the voltage applied to all AVDD pins).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Output propagation delay
tPD
IOH = 1mA, IOL = 1mA
10
20
30
ns
Output enable time
tPZE
15
ns
Output disable time
tPEZ
15
ns
Note: Parameters are measured at 50% of the rising/falling edge.
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
10
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