XWM8148CFT/V 查看數據表（PDF） - Wolfson Microelectronics plc
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XWM8148CFT/V Datasheet PDF : 43 Pages
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WM8148
Production Data
PIN NAME
22
NC
TYPE
DESCRIPTION
No internal connection.
23
NC
No internal connection.
24 DGND2
Ground
Digital ground (0V) for output drivers.
25 AGND4
Ground
Analogue ground (0V).
26 DGND4
Ground
Digital ground (0V).
27 AVDD3
Supply
Analogue supply (5V).
28 AVDD2
Supply
Analogue supply (5V).
29
VRB
Analogue output Lower reference voltage. This pin must be connected to AGND and VRT via decoupling
capacitors. See Recommended External Components section for details.
30 AGND3
Ground
Analogue ground (0V).
31
VRT
Analogue output Upper reference voltage. This pin must be connected to AGND and VRB via decoupling
capacitors. See Recommended External Components section for details.
32
VRX
Analogue output Input return bias voltage. This pin must be connected to AGND via decoupling
capacitors. See Recommended External Components section for details.
33
VRLC
Analogue IO
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
See Recommended External Components section for details. VRLC can be externally
driven if programmed Hi-Z.
34
OVRD
Analogue input Override pin. Typically tied low externally.
The sense of this pin defines the device function on reset. Refer to the description of
pin 42 for details.
35 AGND1
Ground
Analogue ground (0V).
36
RINP
Analogue input Red channel input video.
37
GINP
Analogue input Green channel input video.
38
NC
No internal connection.
39
BINP
Analogue input Blue channel input video.
40 AGND2
Ground
Analogue ground (0V).
41 AVDD1
Supply
Analogue supply (5V).
42 NRESET
Digital input
Reset input, active low. This signal forces a reset of all internal registers.
Registers are set to defaults if pin OVRD is tied low.
If pin OVRD is tied high then all registers are set to defaults except EN which is set to
1 and RLCEXT which is set to 0. This will turn on all analogue circuitry including the RLC
DAC buffers driving the VRLC pin.
43
OEB
Digital input
Output enable control, all outputs disabled when OEB = 1.
This pin must be externally connected.
44
SDO
Digital output
Serial Interface: register read-back,
VSMP output, setup error flag or
over-range flag (depending on control
bits SDO [1:0]).
Parallel Interface: Hi-Z, VSMP output, set-up
error flag or over-range flag (depending on
control bits SDO [1:0]).
45 SDI/DNA
Digital input
Serial interface:
serial input data signal.
Parallel interface: High = data, Low = address.
46 SCK/RNW Digital input Serial interface: serial clock signal.
Parallel interface:
High = OP[11:4] is output bus,
Low = OP[11:4] is input bus (Hi-Z).
47 SEN/STB
Digital input
Serial interface: enable pulse,
active high.
Parallel interface: strobe, active low.
48
PNS
Digital input Low = serial interface, High = parallel interface. This pin must be externally connected.
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
3
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