SL74HC192 查看數據表（PDF） - System Logic Semiconductor
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SL74HC192 Datasheet PDF : 7 Pages
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SL74HC192
AC ELECTRICAL CHARACTERISTICS(CL=50pF,Input tr=tf=6.0 ns)
Symbol
Parameter
fmax Minimum Clock Frequency (50% Duty Cycle)
(Figures 1 and 6)
tPLH, tPHL Maximum Propagation Delay, Clock to Q (Figures
1 and 6)
tPLH, tPHL Maximum Propagation Delay, PL to Q
(Figures 3 and 6)
tPLH, tPHL Maximum Propagation Delay, Clock to Terminal
Count (Figures 2 and 6)
tTLH, tTHL Maximum Output Transition Time,Any Output
(Figures 1 and 6)
CIN
Maximum Input Capacitance
VCC
Guaranteed Limit
V 25 °C to ≤85°C ≤125°C Unit
-55°C
2.0 12
3.2
2.6 MHz
4.5 36
16
13
6.0 43
19
15
2.0 215
270
325
ns
4.5 43
54
65
6.0 37
46
55
2.0 215
270
325
ns
4.5 43
54
65
6.0 37
46
55
2.0 125
155
190
ns
4.5 25
31
38
6.0 21
26
32
2.0 75
95
110
ns
4.5 15
20
23
6.0 13
18
20
-
10
10
10
pF
Power Dissipation Capacitance (Per Package)
CPD Used to determine the no-load dynamic power
consumption: PD=CPDVCC2f+ICCVCC
Typical @25°C,VCC=5.0 V
60
pF
TIMING REQUIREMENTS(CL=50pF,Input tr=tf=6.0 ns)
VCC
Symbol
Parameter
V
tsu
Minimum Setup Time, Pn to PL
2.0
(Figure 4)
4.5
6.0
th
Minimum Hold Time, Pn to PL (Figure 2.0
4)
4.5
6.0
tw
Minimum Pulse Width, Clock (Figure 2.0
1)
4.5
6.0
tw
Minimum Pulse Width, PL
2.0
(Figure 3)
4.5
6.0
tw
Minimum Pulse Width, MR
2.0
(Figure 5)
4.5
6.0
tr, tf Minimum Input Rise and Fall Times
2.0
(Figure 1)
4.5
6.0
Guaranteed Limit
25 °C to -55°C ≤85°C ≤125°C Unit
100
125
150
ns
20
35
30
18
22
26
0
0
0
ns
0
0
0
0
0
0
150
190
225
ns
30
38
45
26
33
38
100
125
150
ns
20
25
30
17
26
26
100
125
150
ns
20
25
30
17
26
26
100
100
100
ns
500
500
500
400
400
400
SLS
System Logic
Semiconductor
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