MSM82C37B-5GS 查看數據表（PDF） - Oki Electric Industry
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MSM82C37B-5GS Datasheet PDF : 34 Pages
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¡ Semiconductor
DMA (Master) Mode (continued)
Symbol
tDCL
tDCTR
tDCTW
tDQ
tEPS
tEPW
tFAAB
tFAC
tFADB
tHS
tIDH
tIDS
tODH
tODV
tQS
tRH
tRS
tSTL
tSTT
Item
Delay Time from CLK Rising Edge
to Read/Write Signal Leading Edge
Delay Time from CLK Rising Edge
to Read Signal Trailing Edge
Delay Time from CLK Rising Edge
to Write Signal Trailing Edge
Delay Time from CLK Rising Edge
to HRQ Valid
EOP Leading Edge Set-up Time to
CLK Falling Edge
EOP Pulse Width
Delay Time from CLK Rising Edge
to Address Valid
Time from CLK Rising Edge
up to Active Read/Write Signal
Delay Time from CLK Rising Edge
to Data Valid
HLDA Valid Set-up Time
to CLK Rising Edge
Input Data Hold Time
to MEMR Trailing Edge
Input Data Set-up
to MEMR Trailing Edge
Output Data Hold Time
to MEMW Trailing Edge
Time from Output Data Valid
to MEMW Trailing Edge
DREQ Set-up Time
to CLK Falling Edge
READY Hold Time
to CLK Falling Edge
READY Set-up Time
to CLK Falling Edge
Delay Time from CLK Rising Edge
to ADSTB Leading Edge
Delay Time from CLK Rising Edge
to ADSTB Trailing Edge
MSM82C37B-5RS/GS/VJS
Min.
—
—
—
—
40
220
—
—
—
75
0
170
10
125
0
20
60
—
—
Max.
190
190
130
120
—
—
170
150
200
—
—
—
—
—
—
—
—
130
90
Unit
Comments
ns
(Note 2)
ns
(Note 2)
ns
(Note 2)
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
—
ns
(Note 3)
ns
—
ns
—
ns
—
ns
—
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