MSM82C59A-2RS 查看數據表（PDF） - Oki Electric Industry

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MSM82C59A-2RS

PROGRAMMABLE INTERRUPT CONTROLLER

Oki Electric Industry 

¡ Semiconductor

MSM82C59A-2RS/GS/JS

(v) A further two INTA pulses are then sent to the MSM82C59A-2 from the CPU by this

CALL instruction.

(vi) These two INTA pulses result in a preprogrammed subroutine address being sent from

the MSM82C59A-2 to the data bus. The lower 8-bit address is released by the first INTA

pulse, and the higher 8-bit address is released by the second pulse.

The Falling Edge of the second INTA signal sets the ISR bit with the highest priority,

and the Rising Edge of it resets the IRR bit.

(vii) 3-byte CALL instructions are thus released by the MSM82C59A-2. In Automatic End

Of Interrupt (AEOI) mode, the IRS bit is reset at the end of the third INTA pulse. In other

cases, the ISR bit remains set until reception of a suitable EOI command at the end of

the interrupt routine.

The procedure for the 86 system (MSM80C86A-10/88A-10) is identical to the first three

steps of the 85 system. The subsequent steps are described below.

(iv) Upon reception of the INTA signal from the CPU, the ISR bit with the highest priority

is set, and the corresponding IRR bit is reset. In this cycle, the MSM82C59A-2 sets the

data bus to high impedance without driving the Data Bus.

(v) The CPU generates a second INTA output pulse, resulting in an 8-bit pointer to the data

bus by the MSM82C59A-2.

The Falling Edge of the INTA signal sets the ISR bit with the highest priority, and the

Rising Edge of it resets the IRR bit.

(vi) This completes the interrupt cycle. In AEOI mode, the ISR bit is reset at the end of the

second INTA pulse. In other cases, the ISR bit remains set until reception of 3 suitable

EOI command at the end of the interrupt routine.

If the interrupt request is canceled prior to step (iv), that is, before the first INTA pulse has

been received, the MSM82C59A-2 operates as if a level 7 interrupt has been received, and

the vector byte and CAS line operate as if a level 7 interrupt has been requested.

(3) Interrupt Sequence Output

85 Mode (MSM80C85AH)

The sequence in this case consists of three INTA pulses. A CALL operation code is released

to the data bus by the first INTA pulse.

CALL Code

Contents of the First Interrupt Vector Byte

D7 D6 D5 D4 D3

1 10 01

D2 D1 D0

10 1

The lower address of the interrupt service routine is released to the data bus by the second

INTApulse. If A5-A7 are programmed with an address interval of 4, A0-A4 are automatically

inserted. And if A6 and A7 are programmed at an address interval of 8, A0-A5 are

automatically inserted.

Contents of the second interrupt vector byte

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