MSM82C59A-2RS 查看數據表（PDF） - Oki Electric Industry
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MSM82C59A-2RS Datasheet PDF : 28 Pages
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¡ Semiconductor
MSM82C59A-2RS/GS/JS
PIN FUNCTION DESCRIPTION
Pin Symbol Name Input/Output
Function
D7 - D0
CS
Bidirectional
Data Bus
Chip Select
Input
Input/Output
Input
This 3-state 8-bit bidirectional data bus is used in reading status
registers and writing command words through the RD/WR signal
from the CPU, and also in reading the CALL instruction code by the
INTA signal from the CPU.
Data transfer with the CPU is enabled by RD/WR when this pin is at
low level. The data bus (D0 thru D7) is switched to high impedance
when the pin is at high level. Note that CS does not effect INTA.
RD
WR
A0
CAS0 - 2
Read Input
Write Input
Address
Input
Cascade
Address
Input
Input
Input
Input/Output
Data is transferred from the MSM82C59A-2 to the CPU when this pin
is at low level. IRR (Interrupt Request Register), ISR (In-Service
Register), IMR (Interrupt Mask Register), or a Poll word is selected
by OCW3 and A0.
Commands are transferred from the CPU to the MSM82C59A-2 when
this pin is at low level.
This pin is used together with the CS, WR, and RD signals to write
commands in the command registers, and to select and read status
registers. This is normally connected to the least significant bit of the
address bus. (A0 for MSM80C85AH, A1 for MSM80C86A-10/88A-10).
These pins are outputs when the MSM82C59A-2 is used as the
master, and inputs when used as a slave (in cascade mode). These
pins are outputs when in single mode.
SP/EN
INT
Slave Program
Input/Enable Input/Output
Buffer Output
This dual function pin is used as an output to enable the data bus
buffer in Buffered mode, and as an input for deciding whether the
MSM82C59A-2 is to be master (SP/EN = 1) or slave (SP/EN =0)
during Non-buffered mode.
Interrupt
Output
Output
When an interrupt request is made to the MSM82C59A-2, the INT
output is switched to high level, and INT interrupt is sent to the CPU.
Interrupt
When this pin is at low level, the CALL instruction code or the
INTA
Acknowledge
Input
Input
interrupt vector data is enabled onto the data bus. When the CPU
acknowledges the INT interrupt, INTA is sent to the MSM82C59A-2.
(Interrupt acknowledge sequence).
IR0 - 7
Request
Input
Input
These interrupt request input pins for the MSM82C59A-2 can be set
to edge trigger mode or level trigger mode ( by ICW1). In edge trigger
mode, interrupt request is executed by the rising edge of the IR input
and holds it until that input is acknowledged by the CPU. In level
trigger mode, interrupt requests are executed by high level IR inputs
and holds them until that input is acknowledged by the CPU. These
pins have a pull up resistor.
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