MSM82C59A-2RS 查看數據表（PDF） - Oki Electric Industry
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MSM82C59A-2RS Datasheet PDF : 28 Pages
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¡ Semiconductor
MSM82C59A-2RS/GS/JS
SYSTEM INTERFACE
Address Bus
Control Bus
Cascade
Address Bus
Data Bus
8 bits
CS A0 D7 - D0 RD WR INT INTA
CAS0
CAS1
MSM82C59A-2
CAS2
SP/EN IR0 IR1 IR2 IR3 IR4 IR5 IR6 IR7
Slave
Program/Enable
Buffer
Interrupt Requests
BASIC OPERATION DESCRIPTION
Data transfers between the 82C59A-2 internal registers and the data bus are listed below.
A0 D4 D3 RD WR CS
Function
0
¥
¥
0
1
0 IRR, ISR, or Poll Word Æ Data Bus
Opearation
Read
1
¥
¥
0
1
0 IMR Æ Data bus
Read
0
0
0
1
0
0 Data Bus Æ OCW2
Write
0
0
1
1
0
0 Data Bus Æ OCW3
Write
0
1
¥
1
0
0 Data Bus Æ 1CW1
Write
1
¥
¥
1
0
0 Data Bus Æ OCW1, ICW2, ICW3, ICW4
¥
¥
¥
1
1
0
Data Bus Set to High Impedance (when INTA = 1)
¥
¥
¥
¥
¥
1
¥
¥
¥
0
0
¥
Combinations Prohibited
Write
—
—
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