AD8005ART-REEL 查看數據表（PDF） - Analog Devices
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AD8005ART-REEL Datasheet PDF : 12 Pages
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AD8005
Single-Ended-to-Differential Conversion
Many single supply ADCs have differential inputs. In such cases,
the ideal common-mode operating point is usually halfway
between supply and ground. Figure 31 shows how to convert a
single-ended bipolar signal into a differential signal with a
common-mode level of 2.5 V.
BIPOLAR
SIGNAL
؎0.5V
+5V
2.49k⍀
0.1F
RIN
1k⍀
2.49k⍀
+5V
0.1F
AD8005
RF1
2.49k⍀
RG
619⍀
RF2
3.09k⍀
+5V
0.1F
+5V
2.49k⍀
AD8005
VOUT
2.49k⍀
0.1F
Figure 31. Single-Ended-to-Differential Converter
Amp 1 has its +input driven with the ac-coupled input signal
while the +input of Amp 2 is connected to a bias level of +2.5 V.
Thus the –input of Amp 2 is driven to virtual +2.5 V by its
output. Therefore, Amp 1 is configured for a noninverting gain
of five, (1 + RF1/RG), because RG is connected to the virtual
+2.5 V of Amp 2’s –input.
When the +input of Amp 1 is driven with a signal, the same
signal appears at the –input of Amp 1. This signal serves as an
input to Amp 2 configured for a gain of –5, (–RF2/RG). Thus the
two outputs move in opposite directions with the same gain and
create a balanced differential signal.
This circuit can be simplified to create a bipolar in/bipolar out
single-ended to differential converter. Obviously, a single supply
is no longer adequate and the –VS pins must now be powered
with –5 V. The +input to Amp 2 is tied to ground. The ac
coupling on the +input of Amp 1 is removed and the signal can
be fed directly into Amp 1.
Layout Considerations
In order to achieve the specified high-speed performance of the
AD8005 you must be attentive to board layout and component
selection. Proper RF design techniques and selection of compo-
nents with low parasitics are necessary.
The PCB should have a ground plane that covers all unused
portions of the component side of the board. This will provide a
low impedance path for signals flowing to ground. The ground
plane should be removed from the area under and around the
chip (leave about 2 mm between the pin contacts and the
ground plane). This helps to reduce stray capacitance. If both
signal tracks and the ground plane are on the same side of the
PCB, also leave a 2 mm gap between ground plane and track.
RG
RF
RO
VIN
RT
C1
0.01F
C2
0.01F
C3
10F
C4
10F
INVERTING CONFIGURATION
RG
RF
RO
VOUT
+VS
–VS
VOUT
VIN
RT
+VS
C1
C3
0.01F
10F
C2
C4
0.01F
10F
–VS
NONINVERTING CONFIGURATION
Figure 32. Inverting and Noninverting Configurations
Chip capacitors have low parasitic resistance and inductance
and are suitable for supply bypassing (see Figure 32). Make sure
that one end of the capacitor is within 1/8 inch of each power
pin with the other end connected to the ground plane. An
additional large (0.47 µF–10 µF) tantalum electrolytic capacitor
should also be connected in parallel. This capacitor supplies
current for fast, large signal changes at the output. It must not
necessarily be as close to the power pin as the smaller capacitor.
Locate the feedback resistor close to the inverting input pin in
order to keep the stray capacitance at this node to a minimum.
Capacitance variations of less than 1.5 pF at the inverting input
will significantly affect high-speed performance.
Use stripline design techniques for long signal traces (i.e., greater
than about 1 inch). Striplines should have a characteristic
impedance of either 50 Ω or 75 Ω. For the Stripline to be
effective, correct termination at both ends of the line is necessary.
Table I. Typical Bandwidth vs. Gain Setting Resistors
Gain
–1
–10
+1
+2
+10
RF
1.49 kΩ
1 kΩ
2.49 kΩ
2.49 kΩ
499 Ω
RG
1.49 kΩ
100 Ω
ؕ
2.49 kΩ
56.2 Ω
RT
52.3
100 Ω
49.9 Ω
49.9 Ω
49.9 Ω
Small Signal –3 dB
BW (MHz),
VS = ؎5 V
120 MHz
60 MHz
270 MHz
170 MHz
40 MHz
–10–
REV. A
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