LTC1045(Rev_B) 查看數據表（PDF） - Linear Technology
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LTC1045 Datasheet PDF : 20 Pages
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LTC1045
APPLICATIONS INFORMATION
The LTC1045 consists of six voltage translators and
associated control circuitry (see Block Diagram). Each
translator has a linear comparator input stage with the
positive input brought out separately. The negative inputs
of the first four comparators are tied in common to VTRIP1
and the negative inputs of the last two comparators are
tied in common to VTRIP2. With these inputs the switching
point of the comparators can be set anywhere within the
common mode range of V – to V + – 2V. To improve noise
immunity each comparator has a small built-in hysteresis.
Hysteresis varies with bias current from 7mV at low bias
current to 20mV at high bias current (see typical curve of
Hysteresis vs RSET).
Setting the Bias Current
Unlike CMOS logic, any linear CMOS circuit must draw
some quiescent current. The bias generator (Block Dia-
gram) allows the quiescent current of the comparators to
be varied. Bias current is programmed with an external
resistor (see typical curve of I + vs RSET). As the bias
current is decreased, the LTC1045 slows down (see
typical curve of Delay Time vs RSET).
Shutting Power Off and Latching the Outputs
In addition to setting the bias current, the ISET pin shuts
power completely off and latches the translator outputs.
To do this, the ISET pin must be forced to V + – 0.5V. As
shown in Figure 4, a CMOS gate or a TTL gate with a
resistor pull-up does this quite nicely. Even though power
is turned off to the linear circuitry, the CMOS output logic
is powered and maintains the output state. With no DC
load on the output, power dissipation, for all practical
purposes, is zero.
Latching the output is fast—typically 80ns from the rising
edge of ISET. Going from the latched to flow-through state
is much slower—typically 1.5µs from the falling edge of
ISET. This time is set by the comparator’s power-up time.
During the power-up time, the output can assume false
states. To avoid problems, the output should not be
considered valid until 2µs to 5µs after the falling edge of
ISET.
Putting the Outputs in Hi-Z State
A DISABLE input sets the six outputs to a high impedance
state. This allows the LTC1045 to be interfaced to a data
bus. When DISABLE = “1” the outputs are high impedance
and when DISABLE = “0” they are active. With TTL
supplies, V + = 4.5V to 5.5V and V – = GND, the DISABLE
input is TTL compatible.
Power Supplies
There are four power supplies on the LTC1045: V +, V –,
VOH and VOL. They can be connected almost arbitrarily, but
there are a few restrictions. A minimum differential must
exist between V + and V – and VOH and VOL. The V + to V –
differential must be at least 4.5V and the VOH to VOL
differential must be at least 3V. Another restriction is
caused by the internal parasitic diode D1 (see Figure 5).
V+
4.5V TO 15V
20
V+
20 4.5V TO 5.5V
LTC1045
12
10
(A) CMOS
LTC1045
100k
12
10
(B) TTL
1045 F04
V+
DISABLE
VOL
DATA
V+
DISABLE
VOL
VOH
V+
D1
P1
N1
VOL
OUTPUT
PIN
1045 F05
Figure 4. Driving the ISET Pin with Logic
Figure 5. Output Driver
6
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