74HCT157U 查看數據表（PDF） - Philips Electronics

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74HCT157U

Quad 2-input multiplexer

Philips Electronics 

Philips Semiconductors

Quad 2-input multiplexer

Product specification

74HC/HCT157

FEATURES

• Non-inverting data path

• Output capability: standard

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT157 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT157 are quad 2-input multiplexers which

select 4 bits of data from two sources under the control of

a common data select input (S). The four outputs present

the selected data in the true (non-inverted) form. The

enable input (E) is active LOW. When E is HIGH, all of the

outputs (1Y to 4Y) are forced LOW regardless of all other

input conditions.

Moving the data from two groups of registers to four

common output buses is a common use of the “157”. The

state of the common data select input (S) determines the

particular register from which the data comes. It can also

be used as function generator.

The device is useful for implementing highly irregular logic

by generating any four of the 16 different functions of two

variables with one variable common.

The “157” is the logic implementation of a 4-pole,

2-position switch, where the position of the switch is

determined by the logic levels applied to S.

The logic equations are:

1Y = E.(1l1.S + 1l0.S)

2Y = E.(2l1.S + 2l0.S)

3Y = E.(3l1.S + 3l0.S)

4Y = E.(4l1.S + 4l0.S)

The “157” is identical to the “158” but has non-inverting

(true) outputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns

SYMBOL

tPHL/ tPLH

CI

CPD

PARAMETER

CONDITIONS

propagation delay

nI0, nI1 to nY

E to nY

CL = 15 pF; VCC = 5 V

S to nY

input capacitance

power dissipation capacitance per multiplexer notes 1 and 2

TYPICAL

HC HCT

11 13

11 12

12 19

3.5 3.5

70 70

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

UNIT

ns

ns

ns

pF

pF

ORDERING INFORMATION

See “74HC/HCT/HCU/HCMOS Logic Package Information”.

December 1990

2

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