MC74HC173AD 查看數據表（PDF） - Motorola => Freescale
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MC74HC173AD Datasheet PDF : 7 Pages
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 3-State D Flip-Flop with
Common Clock and Reset
High–Performance Silicon–Gate CMOS
MC74HC173A
The MC74HC173A is identical in pinout to the LS173. The device inputs
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
Data, when enabled, are clocked into the four D flip–flops with the rising
edge of the common Clock. When either or both of the Output Enable
Controls is high, the outputs are in a high–impedance state. This feature
allows the HC173A to be used in bus–oriented systems. The Reset feature
is asynchronous and active high.
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity 208 FETs or 52 Equivalent Gates
N SUFFIX
16–LEAD PLASTIC DIP PACKAGE
CASE 648–08
D SUFFIX
16–LEAD PLASTIC SOIC PACKAGE
CASE 751B–05
ORDERING INFORMATION
MC74HCXXXAN
MC74HCXXXAD
Plastic
SOIC
LOGIC DIAGRAM
DATA
INPUTS
D0 14
D1 13
D2 12
D3 11
CLOCK 7
DATA–
ENABLES
DE1 9
DE2 10
RESET 15
OUTPUT OE1 1
ENABLES OE2 2
3 Q0
4 Q1
5 Q2
6 Q3
3–STATE
NONINVERTING
OUTPUTS
PIN ASSIGNMENT
OE1 1
OE2 2
Q0 3
Q1 4
Q2 5
Q3 6
CLOCK 7
GND 8
16 VCC
15 RESET
14 D0
13 D1
12 D2
11 D3
10 DE2
9 DE1
VCC = PIN 16
GND = PIN 8
Output Enables
OE1 OE2
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
H
Reset
H
L
L
L
L
L
L
L
X
X
X
FUNCTION TABLE
Inputs
Data Enables
Clock DE1 DE2
X
X
X
L
X
X
H
X
X
H
X
X
H
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
Output
Data
D
X
X
X
X
X
L
H
X
X
X
X
Q
L
No Change
No Change
No Change
No Change
L
H
No Change
High Impedance
High Impedance
High Impedance
6/97
© Motorola, Inc. 1997
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