MC74HC173AD 查看數據表（PDF） - Motorola => Freescale
零件编号
产品描述 (功能)
生产厂家
MC74HC173AD Datasheet PDF : 7 Pages
| |||
MC74HC173A
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Guaranteed Limit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Symbol
Parameter
VCC
V
v v – 55 to
25_C
85_C
125_C Unit
tsu
Minimum Setup Time, Input D or DE to Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 4)
2.0
100
125
150
ns
3.0
75
100
125
4.5
20
25
30
6.0
17
21
26
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ th
Minimum Hold Time, Clock to Input D or DE
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 4)
2.0
3
3
3
ns
3.0
3
3
3
4.5
3
3
3
6.0
3
3
3
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ trec
Minimum Recovery Time, Reset Inactive to Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 2)
2.0
90
3.0
70
4.5
18
6.0
15
115
135
ns
95
115
23
27
20
23
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tw
Minimum Pulse Width, Clock
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 1)
2.0
80
3.0
65
4.5
16
6.0
14
100
120
ns
90
110
20
24
17
20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tw
Minimum Pulse Width, Reset
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 2)
2.0
80
3.0
65
4.5
16
6.0
14
100
120
ns
90
110
20
24
17
20
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tr, tf
Maximum Input Rise and Fall Times
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ (Figure 1)
2.0
1000
1000
1000
ns
3.0
800
800
800
4.5
500
500
500
6.0
400
400
400
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
INPUTS
D0, D1, D2, D3 (Pins 14, 13, 12, 11)
4–bit data inputs. Data on these pins, when enabled by the
Data–Enable Controls, are entered into the flip–flops on the
rising edge of the clock.
CLOCK (Pin 7)
Clock input.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 3, 4, 5, 6)
3–state register outputs. During normal operation of the
device, the outputs of the D flip–flops appear at these pins.
During 3–state operation, these outputs assume a high–
impedance state.
CONTROL INPUT
Reset (Pin 15)
Asynchronous reset input. A high level on this pin resets all
flip–flops and forces the Q outputs low, if they are not already
in high–impedance state.
DE1, DE2 (Pins 9, 10)
Active–low Data Enable Control inputs. When both Data
Enable Controls are low, data at the D inputs are loaded into
the flip–flops with the rising edge of the Clock input. When
either or both of these controls are high, there is no change in
the state of the flip–flops, regardless of any changes at the D
or Clock inputs.
OE1, OE2 (Pins 1, 2)
Output Enable Control inputs. When either or both of the
Output Enable Controls are high, the Q outputs of the device
are in the high–impedance state. When both controls are
low, the device outputs display the data in the flip–flops.
MOTOROLA
4
High–Speed CMOS Logic Data
DL129 — Rev 6
Share Link: 