MC74HC125ADTEL 查看數據表（PDF） - ON Semiconductor
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MC74HC125ADTEL Datasheet PDF : 8 Pages
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MC74HC125A,
MC74HC126A
Quad 3-State Noninverting
Buffers
High–Performance Silicon–Gate CMOS
The MC74HC125A and MC74HC126A are identical in pinout to
the LS125 and LS126. The device inputs are compatible with standard
CMOS outputs; with pullup resistors, they are compatible with
LSTTL outputs.
The HC125A and HC126A noninverting buffers are designed to be
used with 3–state memory address drivers, clock drivers, and other
bus–oriented systems. The devices have four separate output enables
that are active–low (HC125A) or active–high (HC126A).
• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates
LOGIC DIAGRAM
HC125A
HC126A
Active–Low Output Enables
Active–High Output Enables
A1
2
3
Y1
A1
2
3
Y1
OE1
1
5
A2
OE1
1
6
5
Y2
A2
6
Y2
OE2
4
9
A3
OE2
4
8 Y3
A3
9
8
Y3
OE3
10
12
A4
OE3
10
11
12
Y4
A4
13
OE4
13
OE4
PIN 14 = VCC
PIN 7 = GND
FUNCTION TABLE
HC125A
Inputs Output
A OE Y
HL
H
LL
L
XH
Z
HC126A
Inputs Output
A OE Y
HH H
LH
L
XL
Z
11
Y4
http://onsemi.com
PDIP–14
N SUFFIX
CASE 646
SOIC–14
D SUFFIX
CASE 751A
MARKING
DIAGRAMS
14
MC74HC12xAN
AWLYYWW
1
14
HC12xA
AWLYWW
1
14
TSSOP–14
DT SUFFIX
CASE 948G
HC
12xA
ALYW
1
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
PIN ASSIGNMENT
OE1 1
A1 2
Y1 3
OE2 4
A2 5
Y2 6
GND 7
14 VCC
13 OE4
12 A4
11 Y4
10 OE3
9 A3
8 Y3
ORDERING INFORMATION
Device
Package Shipping
MC74HC12xAN
PDIP–14 2000 / Box
MC74HC12xAD
SOIC–14
55 / Rail
MC74HC12xADR2
SOIC–14 2500 / Reel
MC74HC12xADT
TSSOP–14 96 / Rail
MC74HC12xADTR2 TSSOP–14 2500 / Reel
© Semiconductor Components Industries, LLC, 2000
1
March, 2000 – Rev. 9
Publication Order Number:
MC74HC125A/D
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