SK100E116PJ(2001) 查看數據表（PDF） - Semtech Corporation
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SK100E116PJ Datasheet PDF : 4 Pages
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HIGH-PER.ORMANCE PRODUCTS
Description
.eatures
SK10/100E116
Quint Differential
Line Receiver
The SK10/100E116 is a quint differential line receiver
designed for use in new, high-performance ECL systems.
The receiver design features clamp circuitry to cause a
defined output state if both the inverting and non-inverting
inputs are left open; in this case the Q output goes low,
while the Q* output goes high. This feature makes the
device ideal for twisted pair applications.
If both inverting and non-inverting inputs are at an equal
potential of >–2.9V, the receiver does not go to a defined
state, but rather shares current in normal differential
amplifier fashion, producing output voltage levels midway
between high and low. This may even cause the device to
oscillate.
• 500 ps Maximum Propagation Delay
• Extended VEE Range of –4.2V to –5.5V
• VBB Output for Single-Ended Reception
• Internal 75KΩ Input Pull-Down Resistors
• ESD Protection of >4000V
• Fully Compatible with MC10E/100E116
• Specified Over Industrial Temperature Range:
–40oC to +85oC
• Available in 28-Pin PLCC Package
PIN Description
The SK10/100E116 provides VBB output for either single-
ended use or as a DC bias for AC coupling to the device.
The VBB output pin should be used only as a DC bias for
the E116 as its current sink/source capability is limited.
Whenever used, the VBB pin should be bypassed to VCC
via a 0.01 µF capacitor.
Pin
D0, D0*D4, D4*
Q0, Q0*-Q4, Q4*
VBB
VCC0
.unction
Differential Input Pairs
Differential Output Pairs
Reference Voltage Output
VCC to Output
.unctional Block Diagram
D0
D0*
D1
D1*
D2
D2*
D3
D3*
D4
D4*
VBB
Revision 1 /.ebruary 21, 2001
Q0
Q0*
Q1
Q1*
Q2
Q2*
Q3
Q3*
Q4
Q4*
D3*
26
D2
27
D2*
28
VEE
1
VBB
2
D0
3
D0*
4
PLCC
TOPVIEW
18
Q3*
17
Q3
16
VCC
15
Q2*
14
Q2
13
VCC0
12
Q1*
1
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