CD40102BMS 查看數據表（PDF） - Intersil

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CD40102BMS

CMOS 8-Stage Presettable Synchronous Down Counters

Intersil 

Specifications CD40102BMS, CD40103BMS

TABLE 6. APPLICABLE SUBGROUPS (Continued)

CONFORMANCE GROUP

MIL-STD-883

METHOD

GROUP A SUBGROUPS

Group D

Sample 5005

1, 2, 3, 8A, 8B, 9

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

READ AND RECORD

Subgroups 1, 2 3

CONFORMANCE GROUPS

Group E Subgroup 2

TABLE 7. TOTAL DOSE IRRADIATION

MIL-STD-883

METHOD

TEST

PRE-IRRAD

POST-IRRAD

5005

1, 7, 9

Table 4

READ AND RECORD

PRE-IRRAD

POST-IRRAD

1, 9

Table 4

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR

FUNCTION

OPEN

GROUND

PART NUMBER CD40102BMS, CD40103BMS

VDD

9V ± -0.5V

50kHz

25kHz

Static Burn-In 1

14

1 - 13, 15

16

Note 1

Static Burn-In 2

14

Note 1

8

1 - 7, 9 - 13, 15, 16

Dynamic Burn-

-

In Note 1

3, 8, 15

2, 16

14

1, 4, 6, 11, 13

5, 7, 9, 10, 12

Irradiation

-

Note 2

NOTES:

1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V

2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

VDD = 10V ± 0.5V

Functional Diagram

SPE

APE

CI/CE

CLR

JAM

J0

J7

CLOCK

8 - STAGE

DOWN

COUNTER

C0/ZD

CD40102BMS, CD40103BMS

7-1299

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