CD4518 查看數據表（PDF） - Intersil
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CD4518 Datasheet PDF : 10 Pages
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Logic Diagrams
VDD
CD4518BMS, CD4520BMS
Q1
3/11
Q2
4/12
Q3
5/13
Q4
6/14
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
RESET *
7/15
VSS
ENABLE *
2/10
CLOCK *
1/9
DQ
CQ
R
DQ
CQ
R
DQ
CQ
R
DQ
CQ
R
FIGURE 1. DECADE COUNTER (CD4518BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
VDD
Q1
3/11
Q2
4/12
Q3
5/13
Q4
6/14
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
VSS
RESET *
7/15
DQ
CQ
R
DQ
CQ
R
DQ
CQ
R
DQ
CQ
R
ENABLE *
2/10
CLOCK *
1/9
FIGURE 2. BINARY COUNTER (CD4520BMS) LOGIC DIAGRAM FOR ONE OF TWO IDENTICAL COUNTERS
CLOCK
0
X
1
X
X = Don’t Care
TRUTH TABLE
ENABLE
RESET
1
0
0
X
0
0
0
0
0
X
1
1 ≡ High State 0 ≡ Low State
ACTION
Increment Counter
Increment Counter
No Change
No Change
No Change
No Change
Q1 thru Q4 = 0
7-1211
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