ADM1024ARUZ-REEL7 查看數據表（PDF） - Analog Devices

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ADM1024ARUZ-REEL7

System Hardware Monitor with Remote Diode Thermal Sensing

Analog Devices 

ADM1024

THE ADM1024 INTERRUPT STRUCTURE

The Interrupt Structure of the ADM1024 is shown in Figure 14.

As each measurement value is obtained and stored in the

appropriate value register, the value and the limits from the

corresponding limit registers are fed to the high and low limit

comparators. The result of each comparison (1 = out of limit,

0 = in limit) is routed to the corresponding bit input of the

Interrupt Status Registers via a data demultiplexer and used

to set that bit high or low as appropriate.

The Interrupt Mask Registers have bits corresponding to each

of the Interrupt Status Register Bits. Setting an Interrupt Mask

Bit high forces the corresponding Status Bit output low, while

setting an Interrupt Mask Bit low allows the corresponding

Status Bit to be asserted. After masking, the status bits are all

OR’d together to produce the INT output, which will pull

low if any unmasked status bit goes high, i.e., when any mea-

sured value goes out of limit. The ADM1024 also has a

dedicated output for temperature interrupts only, the THERM

input/output Pin 2. The function of this is described later.

The INT output is enabled when Bit 1 of Configuration Regis-

ter 1 (INT_Enable) is high, and Bit 3 (INT_Clear) is low.

The INT pin has an internal, 100 kΩ pull-up resistor.

VID/IRQ INPUTS

The processor voltage ID inputs VID0 to VID4 can be

reconfigured as interrupt inputs by setting Bit 7 of the Channel

Mode Register (address 16h). In this mode they operate as level-

triggered interrupt inputs, with VID0/IRQ0 to VID2/IRQ2

being active low and VID3/IRQ3 and VID4/IRQ4 being ac-

tive high. The individual interrupt inputs can be enabled or

masked by setting or clearing Bits 4 to 6 of the Channel Mode

Register and Bits 6 and 7 of Configuration Register 2 (address

4Ah). These interrupt inputs are not latched in the ADM1024,

so they do not require clearing as do bits in the Status Registers.

However, the external interrupt source should be cleared once

the interrupt has been serviced, or the interrupt request will be

reasserted.

INTERRUPT CLEARING

Reading an Interrupt Status Register will output the contents of

the Register, then clear it. It will remain cleared until the moni-

toring cycle updates it, so the next read operation should not be

performed on the register until this has happened, or the result

will be invalid. The time taken for a complete monitoring cycle

is mainly dependent on the time taken to measure the fan speeds,

as described earlier.

The INT output is cleared with the INT_Clear bit, which is

Bit 3 of the Configuration Register, without affecting the con-

tents of the Interrupt (INT) Status Registers.

INTERRUPT STATUS MIRROR REGISTERS

Whenever a bit in one of the Interrupt Status Registers is updated,

the same bit is written to duplicate registers at addresses 4Ch

and 42h. These registers allow a second management system to

access the status data without worrying about clearing the data.

The data in these registers is for reading only and has no effect

on the interrupt output.

TEMPERATURE INTERRUPT MODES

The ADM1024 has two distinct methods of producing interrupts

for out-of-limit temperature measurements from the internal or

external sensors. Temperature errors can generate an interrupt

on the INT pin along with other interrupts, but there is also a

separate THERM pin that generates an interrupt only for

temperature errors.

Operation of the INT output for temperature interrupts is illus-

trated in Figure 15. Assuming that the temperature starts off

within the programmed limits and that temperature interrupt

sources are not masked, INT will go low if the temperature

measured by any of the internal or external sensors exceeds the

programmed high temperature limit for that sensor, or the hard-

ware limits in register 13h, 14h, 17h, or 18h.

100؇C

90؇C

*

80؇C

* HIGH LIMIT

70؇C

*

TEMP

*

60؇C

50؇C

*

* LOW LIMIT

40؇C

INT

ACPI CONTROL

METHODS

CLEAR EVENT

*ACPI AND DEFAULT CONTROL METHODS

ADJUST TEMPERATURE LIMIT VALUES

Figure 15. Operation of INT for Temperature Interrupts

Once the interrupt has been cleared, it will not be reasserted

even if the temperature remains above the high limit(s). How-

ever, INT will be reasserted if:

a. the temperature falls below the low limit for the sensor

or

b. the high limit(s) is/are reprogrammed to a new value, and the

temperature then rises above the new high limit on the next

monitoring cycle

or

c. the THERM pin is pulled low externally, which sets Bit 5 of

Interrupt Status Register 2

or

d. an interrupt is generated by another source.

Similarly, should the temperature measured by a sensor start off

within limits then fall below the low limit, INT will be asserted.

Once cleared, it will not be reasserted unless:

a. the temperature rises above the high limit

or

b. the low limit(s) is/are reprogrammed, and the temperature

then falls below the new low limit

or

c. the THERM pin is pulled low externally, which sets Bit 5 of

Interrupt Status Register 2

or

d. an interrupt is generated by another source.

–20–

REV. B

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