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CAT28F010T-90T 查看數據表(PDF) - Catalyst Semiconductor => Onsemi
零件编号
产品描述 (功能)
生产厂家
CAT28F010T-90T
1 Megabit CMOS Flash Memory
Catalyst Semiconductor => Onsemi
CAT28F010T-90T Datasheet PDF : 15 Pages
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CAT28F010
Figure 5. Chip Erase Algorithm
(1)
START ERASURE
APPLY VPPH
PROGRAM ALL
BYTES TO 00H
INITIALIZE
ADDRESS
INITIALIZE
PLSCNT = 0
WRITE ERASE
SETUP COMMAND
WRITE ERASE
COMMAND
BUS
OPERATION
COMMAND
COMMENTS
STANDBY
VPP RAMPS TO VPPH
(OR VPP HARDWIRED)
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
INITIALIZE ADDRESS
PLSCNT = PULSE COUNT
WRITE
ERASE
ACTUAL ERASE
NEE
D
D
A
S
T
1
A
0m
=
s
2
P
0
U
H
LSE,
DATA = 20H
WRITE
ERASE
DATA = 20H
TIME OUT 10ms
WAIT
WRITE ERASE
VERIFY COMMAND
WRITE
ERASE
VERIFY
ADDRESS = BYTE TO VERIFY
DATA = 2
4A
0
00
H
HH
;
;
STOPS ERASE OPERATION
INCREMENT
ADDRESS
TIME OUT 6 s
READ DATA
FROM DEVICE
DATA =
NO
FFH?
YES
NO
LAST
ADDRESS?
YES
WRITE READ
COMMAND
APPLY VPPL
NO
INC PLSCNT
= 3
1
00
0
0
0
?
YES
APPLY VPPL
READ
STANDBY
WAIT
READ BYTE TO
VERIFY ERASURE
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
WRITE
READ
STANDBY
DATA = 00H
RESETS THE REGISTER
FOR READ OPERATION
VPP RAMPS TO VPPL
(OR VPP HARDWIRED)
ERASURE
COMPLETED
ERASE
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 1019, Rev. D
10
5108 FHD F10
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