GLT6400M08LLI-85ST 查看數據表（PDF） - G-Link Technology
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GLT6400M08LLI-85ST Datasheet PDF : 10 Pages
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G-LINK
GLT6400M08
Ultra Low Power 512k x 8 CMOS SRAM
Aug 2001(Rev.3.0)
Timing Waveform of Read Cycle 1 (3,6,7,9) (Address Controlled)
Address
tRC
tAA
tOH
DOUT
Data Valid
Timing Waveform of Read Cycle 2 (5,6,8,9) ( CE1 Controlled)
CE1
tRC
OE
tOE
tACE
tOLZ
tOHZ
tCHZ
DOUT
tCLZ
Data Valid
Supply Current
tPU
50%
tPD
ICC
50%
ISB
Write Cycle (3,11)( Vcc=2.3V to 2.7V, TA =-25°C to + 85°C)
Parameter
Write Cycle Time
Chip Enable to Write End
Address Setup to Write End
Address Setup Time
Write Pulse Width
Write Recovering Time
Data Valid to Write End
Data Hold Time
Write Enable to Output in High-Z
Output Active from Write End
85
Symbol
Min Max
tWC
85
tCW
70
tAW
70
tAS
0
tWP
60
tWR
0
tDW
35
tDH
0
tWZ
35
tOW
5
120
Unit Note
Min Max
120
ns
100
ns
100
ns
0
ns
80
ns
0
ns
50
ns
0
ns
0
35 ns 4,5
5
ns 4,5
G-Link Technology Corporation
2701 Northwestern Parkway
Santa Clara, CA 95051, U.S.A.
-6-
G-Link Technology Corporation, Taiwan
6F No. 24-2, Industry E. RD. IV, Science Based
Industrial Park, Hsin Chu, Taiwan.
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