UT1553BRTSGC 查看數據表（PDF） - Aeroflex UTMC
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UT1553BRTSGC Datasheet PDF : 48 Pages
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Control Register (Write Only)
The 13-bit write-only Control Register manages the operation of the RTS. Write to the Control Register by applying a logic
one to OE, and a logic zero to CTRL, CS, and RD/WR. Data is loaded into the Control Register via I/O pins DATA(12:0).
Control register write must occur 50ns before the rising edge of COMSTR to latch data into the outgoing status word.
Bit
Number
Initial
Condition
Description
Bit 0
[1]
Channel A Enable. A logic 1 enables Channel A biphase inputs.
Bit 1
[1]
Channel B Enable. A logic 1 enables Channel B biphase inputs.
Bit 2
[0]
Terminal Flag. A logic 1 sets the Terminal Flag bit of the Status Word.
Bit 3
[1]
System Busy. A logic 1 sets the Busy bit of the Status Word and limits RTS access to the
memory. No data word can be retrieved or stored; command words will be stored.
Bit 4
[0]
Subsystem Busy. A logic 1 sets the Subsystem Flag bit of the Status Word.
Bit 5
[0]
Self-Test Channel Select. This bit selects which channel the self-test checks; a logic 1 selects
Channel A and a logic 0 selects Channel B.
Bit 6
[0]
Self-Test Enable. A logic 1 places the RTS in the internal self-test mode and inhibits normal
operation. Channels A and B should be disabled if self-test is chosen.
Bit 7
[0]
Service Request. A logic 1 sets the Service Request bit of the Status Word.
Bit 8
[0]
Instrumentation. A logic 1 sets the Instrumentation bit of the Status Word.
Bit 9
[1]
Broadcast Enable. A logic 1 enables the RTS to recognize broadcast commands.
Bit 10
[1]
Notice Select. A logic 1 enables Notice III operation; logic 0 enables Notice I or II operation.
Bit 11
[1]
DSCNCT/TERACT Pin Select. A logic 1 selects the “Disconnect” function; a logic 0 selects
the “Terminal Active” function.
Bit 12
[1]
RBUSY Time Select. A logic 1 selects a 5.7µs RBUSY alert; a logic 0 selects a 2.7µs
RBUSY alert.
[] - Values in parentheses indicate the initialized values of these bits.
CONTROL REGISTER (WRITE ONLY):
X X X RBUSY PS NO BCEN INS SRQ ITST ITCS SUBS BUSY TF
TS
TICE
CH B CH A
EN EN
MSB
[1] [1] [1] [1] [0] [0] [0] [0] [0] [1] [0] [1] [1]
LSB
[ ] defines reset state
Figure 4a. Control Register
RTS-6
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