AME8500AEETCD20 查看數據表（PDF） - AME, Inc

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AME8500AEETCD20

µProcessor Supervisory

AME, Inc 

AME, Inc.

AME8500 / 8501

n Timing Diagram

VDD

RESET

VRelease

RESETB

TD2

TD2

n Applications Information

Supply Transients

These devices have a certain immunity to fast negative

going transients. In the following pages the graph titled

“Glitch Rejection” indicates the maximum allowable glitch

amplitude and duration to avoid triggering an unintended

reset. As shown in the graph shorter transients can have

larger amplitudes without triggering resets.

Glitch Rejection

140

120

100

80

60

40

20

0

0.01

0.1

1

Glitch Amplitude (V)

µProcessor Supervisory

VTH

50%

TD1

50%

50%

TD1

50%

Reset Time vs. Temperature

220

215

210

205

AME8500AEETAF26

200

195

190

-45

-5

25

55

85

115

Temperature (oC)

10

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