RF3321 查看數據表（PDF） - RF Micro Devices
零件编号
产品描述 (功能)
生产厂家
RF3321 Datasheet PDF : 16 Pages
| |||
RF3321
Preliminary
Pin Function Description
Interface Schematic
1
SHDNB Chip shutdown pin. Forcing a logic low causes all circuits to switch off
and gain settings to be lost.
2
TX EN
Signal path enable pin. Logic high turns on signal path. Logic low turns
off signal path, but leaves serial bus active.
3
NC
Not connected.
4
VIN
Input pin. This should be externally AC-coupled to signal source.
VCC
550 Ω
550 Ω
3
500 Ω
VIN
500 Ω
VINB
5
VINB
Complementary input pin. This should be externally coupled to signal See pin 4.
source. For single-ended use, this pin should be AC-coupled to ground.
6
VCC1
This pin is connected to VCC1.
7
VCC1
Same as pin 6.
8
RAMP
External capacitor to ground controls start-up time.
9
SCLK
Serial bus clock input.
10
CS
Serial bus enable.
11
SDA
Serial bus data input.
12
VOUTB Open collector output. Connect to VCC2 via balun primary.
VOUT
VOUTB
300 Ω
RE
13
14
15
16
PKG
BASE
VOUT
NC
NC
GND
GND
Open collector output. Connect to VCC2 via balun primary.
See pin 12.
Same as pin 3.
Same as pin 3.
Connect to ground.
Die is mounted on a heat sink slug that should be connected to ground.
Device grounds are internally bonded to the slug.
Serial Bus Block Diagram
D6
D5
D4
D3
D2
D1
D0
CS
SDA
SCLK
DQ
DQ
D
Q
DQ
D
Q
D
Q
DQ
CK CLR
CK CLR
CK CLR
CK CLR
CK CLR
CK CLR
CK CLR
D
Q
DQ
DQ
D
Q
DQ
D
Q
D
Q
CK CLR
CK CLR
CK CLR
CK CLR
CK CLR
CK CLR
CK CLR
POR
2-4
Rev A10 010516
Share Link: 