AD1890JN 查看數據表（PDF） - Analog Devices

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AD1890JN

SamplePort Stereo Asynchronous Sample Rate Converters

Analog Devices 

AD1890/AD1891

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PRODUCT OVERVIEW (Continued)

automatically limited to avoid alias distortion on the output sig-

nal. The AD1890/AD1891 dynamically alter the low-pass filter

cutoff frequency smoothly and slowly, so that real-time varia-

tions in the sample rate ratio are possible without degradation of

the audio quality.

The AD1890/AD1891 have a pin selectable slow- or fast-settling

mode. This mode determines how quickly the ASRCs adapt to a

change in either the input sample clock frequency (FSIN) or the

output sample clock frequency (FSOUT). In the slow-settling

mode, the control loop which computes the ratio between FSIN

and FSOUT settles in approximately 800 ms and begins to reject

jitter above 3 Hz. The slow-settling mode offers the best signal

quality and the greatest jitter rejection. In the fast-settling mode,

the control loop settles in approximately 200 ms and begins to

reject jitter above 12 Hz. The fast-settling mode allows rapid,

real time sample rate changes to be tracked without error, at the

expense of some narrow-band noise modulation products on the

output signal.

The AD1890 also has a pin selectable, short or long group delay

mode. This pin determines the depth of the First-In, First-Out

(FIFO) memory which buffers the input data samples before

they are processed by the FIR convolver. In the short mode, the

group delay is approximately 700 µs. The ASRC is more sensi-

tive to sample rate changes in this mode (i.e., the pointers which

manage the FIFO are more likely to cross and become momen-

tarily invalid during a sample rate step change), but the group

delay is minimized. In the long mode, the group delay is ap-

proximately 3 ms. The ASRC is tolerant of large dynamic

sample rate changes in this mode, and it should be used when

the device is required to track fast sample rate changes, such as

in varispeed applications. The AD1891 features the short group

delay mode only. In either device, if the read and write pointers

that manage the FIFO cross (indicating underflow or overflow),

the ASRC asserts the mute output (MUTE_O) pin HI for 128

output clock cycles. If MUTE_O is connected to the mute input

(MUTE_I) pin, as it normally should be, the serial output will

be muted (i.e., all bits zero) during this transient event.

The AD1890/AD1891 are fabricated in a 0.8 µm single poly,

double metal CMOS process and are packaged in a 0.6" wide

28-pin plastic DIP and a 28-pin PLCC. The AD1890/AD1891

operate from a +5 V power supply over the temperature range of

0°C to +70°C.

GPDLYS (AD1890)

N/C (AD1891) 1

MCLK 2

DATA_I 3

BCLK_I 4

WCLK_I 5

LR_I 6

SERIAL IN

SERIAL OUT

ACCUM

28 SETSLW

27 GND

26 BCLK_O

25 WCLK_O

24 LR_O

23 DATA_O

VDD 7

GND 8

MULT

22 VDD

21 GND

N/C 9

BKPOL_I 10

TRGLR_I 11

MSBDLY_I 12

RESET 13

GND 14

20 N/C

FIFO

COEF ROM

19 BKPOL_O

18 TRGLR_O

17 MSBDLY_O

CLOCK

16 MUTE_O

TRACKING

15 MUTE_I

AD1890/AD1891

N/C = NO CONNECT

AD1890/AD1891 DIP Pinout

4 3 2 1 28 27 26

WCLK_I 5

SERIAL IN

SERIAL OUT

25 WCLK_O

LR_I 6

VDD 7

GND 8

N/C 9

BKPOL_I 10

ACCUM

MULT

FIFO

COEF ROM

24 LR_O

23 DATA_O

22 VDD

21 GND

20 N/C

TRGLR_I 11

CLOCK

TRACKING

19 BKPOL_O

AD1890/AD1891

12 13 14 15 16 17 18

N/C = NO CONNECT

AD1890/AD1891 PLCC Pinout

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