M41T80(2002) 查看數據表（PDF） - STMicroelectronics

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M41T80
(Rev.:2002)

SERIAL ACCESS RTC WITH ALARMS

STMicroelectronics 

M41T80

READ Mode

In this mode the master reads the M41T80 slave

after setting the slave address (see Figure 10,

page 10). Following the WRITE Mode Control Bit

(R/W=0) and the Acknowledge Bit, the word ad-

dress 'An' is written to the on-chip address pointer.

Next the START condition and slave address are

repeated followed by the READ Mode Control Bit

(R/W=1). At this point the master transmitter be-

comes the master receiver. The data byte which

was addressed will be transmitted and the master

receiver will send an Acknowledge Bit to the slave

transmitter. The address pointer is only increment-

ed on reception of an Acknowledge Clock. The

M41T80 slave transmitter will now place the data

byte at address An+1 on the bus, the master re-

ceiver reads and acknowledges the new byte and

the address pointer is incremented to “An+2.”

Figure 9. Slave Address Location

This cycle of reading consecutive addresses will

continue until the master receiver sends a STOP

condition to the slave transmitter.

The system-to-user transfer of clock data will be

halted whenever the address being read is a clock

address (00h to 07h). The update will resume due

to a Stop Condition or when the pointer increments

to any non-clock address (08h-13h).

Note: This is true both in READ Mode and WRITE

Mode.

An alternate READ Mode may also be implement-

ed whereby the master reads the M41T80 slave

without first writing to the (volatile) address point-

er. The first address that is read is the last one

stored in the pointer (see Figure 11, page 11).

R/W

START

SLAVE ADDRESS

A

11 0100 0

AI00602

Figure 10. READ Mode Sequence

BUS ACTIVITY:

MASTER

SDA LINE

S

WORD

ADDRESS (An)

S

BUS ACTIVITY:

SLAVE

ADDRESS

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+X P

AI00899

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