AM85C30-8PC 查看數據表（PDF） - Advanced Micro Devices
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AM85C30-8PC Datasheet PDF : 68 Pages
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AMD
Enhancements that allow the Am85C30 to be used
more effectively in high-speed applications include:
s A 10 × 19 bit SDLC/HDLC frame status FIFO array
s A 14-bit SDLC/HDLC frame byte counter
s Automatic SDLC/HDLC opening frame flag
transmission
s TxD pin forced High in SDLC NRZI mode after
closing flag
s Automatic SDLC/HDLC Tx underrun/EOM flag
reset
s Automatic SDLC/HDLC Tx CRC generator reset/
preset
s RTS synchronization to closing SDLC/HDLC flag
DTR/REQ deactivation delay significantly reduced
s External PCLK to RxC or TxC synchronization
requirement eliminated for PCLK divide-by-four
operation
BLOCK DIAGRAM
Other enhancements to improve the Am85C30 inter-
face capabilities include:
s Write data valid setup time to falling edge of WR
requirement eliminated
s Reduced INT response time
s Reduced access recovery time (tRC) to 3 PCLK
best case (3 1/2 PCLK worst case)
s Improved Wait timing
s Write Registers WR3, WR4, WR5, and WR10
made readable
s Lower priority interrupt masking without INTACK
s Complete SDLC/HDLC CRC character reception
Data
Control
8
CPU
Bus VO
5
Interrupt
Control Lines
Internal
Control
Logic
Channel
A
Registers
Internal Bus
Interrupt
Control
Logic
Channel
B
Registers
+5 V GND PCLK
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