ST24E16 查看數據表（PDF） - STMicroelectronics

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ST24E16

16 Kbit Serial I2C EEPROM with Extended Addressing

STMicroelectronics 

Figure 9. Write Modes Sequence with Write Control = 1

ST24E16, ST25E16

WC

BYTE WRITE

ACK

ACK

ACK

ACK

DEV SEL

BYTE ADDR BYTE ADDR

DATA IN

R/W

WC

PAGE WRITE

WC (cont'd)

PAGE WRITE

(cont'd)

ACK

ACK

ACK

ACK

DEV SEL

BYTE ADDR BYTE ADDR DATA IN 1

DATA IN 2

R/W

ACK

ACK

DATA IN N

AI01106B

sequence. To terminate the stream of bytes, the

master must NOT acknowledge the last byte out-

put, but MUST generate a STOP condition. The

output data is from consecutive byte addresses,

with the internal byte address counter automat-

ically incremented after each byte output. After a

count of the last memory address, the address

counter will ’roll-over’ and the memory will continue

to output data.

Acknowledge in Read Mode. In all read modes

the ST24/25E16 wait for an acknowledge during

the 9th bit time. If the master does not pull the SDA

line low during this time, the ST24/25E16 terminate

the data transfer and switch to a standby state.

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