NT128S64VH4A0GM-75B 查看數據表（PDF） - Nanya Technology
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NT128S64VH4A0GM-75B
Nanya Technology
NT128S64VH4A0GM-75B Datasheet PDF : 12 Pages
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NT128S64VH4A0GM
128MB : 16M x 64
SDRAM SODIMM
Input/Output Functional Description
Symbol
Type Signal Polarity
Function
Positive The system clock inputs. All of the SDRAM inputs are sampled on the rising edge of
CK0
Input Pulse
Edge their associated clock.
CKE0
Input
Level
Active
High
Activates the SDRAM CK0 signals when high and deactivates them when low. By
deactivating the clocks, CKE0 low initiates the Power Down mode, Suspend mode, or the
Self-Refresh mode.
S0
RAS , CAS , WE
Input
Input
Pulse
Active
Low
Pulse
Active
Low
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.
When sampled at the positive rising edge of the clock, RAS , CAS , WE define the
operation to be executed by the SDRAM.
BA0, BA1
Input Level
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A8 defines the column address (CA0-CA8)
A0 - A9
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high,
A10/AP
A11, A12
Input Level
-
autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low,
autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control
which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the
state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to
pre-charge.
Input
Data and Check Bit input/output pins operate in the same manner as on conventional
DQ0 - DQ63
Level
-
/Output
DRAMs.
The Data input/output mask places the DQ buffers in a high impedance state when
DQMB0 -DQMB7 Input
Pulse
Active
High
sampled high. In Read mode, DQM has a latency of two clock cycles and controls the
output buffers like an output enable. In Write mode, DQM has a latency of zero and
operates as a byte mask by allowing input data to be written if it is low but blocks the
Write operation if DQM is high.
SDA
Serial Data. Bi-directional signal used to transfer data into and out of the Serial Presence
Input
Level
-
Detect EEPROM. Since the SDA signal is Open Drain/Open Collector at the EEPROM, a
/Output
pull-up resistor is required on the system board.
Serial Clock. Used to clock all Serial Presence Detect data into and out of the EEPROM.
SCL
Input Pulse
-
Since the SCL signal is inactive in the “high” state, a pull-up resistor is recommended on
the system board.
VDD , VSS
Supply
Power and ground for the module.
PRELIMINARY 08 /2001
4
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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