NT128S64VH8C0GM 查看數據表（PDF） - Nanya Technology
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NT128S64VH8C0GM
Nanya Technology
NT128S64VH8C0GM Datasheet PDF : 12 Pages
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NT128S64VH8C0GM
128MB : 16M x 64
SDRAM SODIMM
Operating, Standby, and Refresh Currents (TA =0 to 70 °C , VDD =3.3 ± 0.3V)
Parameter
Symbol
Test condition
Speed
Unit Note
- 7K - 75B - 8B
Operating current
1 bank operation , tRC = tRC(mim), tCK = min
ICC1
Active-Precharge Command cycling
without burst operation
720
680
640
mA
1, 2
Precharge
standby current
in power-down mode
ICC2P
ICC2PS
Precharge
standby current in non
power-down mode
ICC2N
ICC2NS
No Operating current
( Active state : 4 bank)
ICC3P
ICC3N
Operating current
( Burst mode )
ICC4
CKE ≤ VIL (max), tCK = min,
S0 , S1= VIH (min)
CKE ≤ VIL (max), tCK =oo,
S0 , S1= VIH (min)
CKE0 ≥ VIH (min), tCK = min
S0 , S1= VIH (min)
CKE ≥ VIH (min), tCK =oo,
S0 , S1= VIH (min)
CKE ≤ VIL (max), tCK =min.
S0 , S1= VIH (min) , (Power Down Mode)
CKE0 ≥ VIH (min), tCK =min
S0 = VIH (min)
tCK =min , Read/ Write command cycling,
Multiple banks active, gapless data, BL=4
16
mA
16
mA
400
360
280
mA
3
72
72
72
mA
4
72
72
72
mA
5
400
400
320
mA
3
810
720
540
mA
2, 6
Auto(CBR)
refresh current
ICC5
tCK =min, CBR command cycling
960
960
860
mA
Self refresh current
ICC6
CKE0 ≤ 0.2V
16
mA
Serial PD Device
Standby Current
ISB
VIN = GND or VDD
30
µA
7
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC . Input signals
are changed up to three times during tRC (min).
2. The specified values are obtained with the output open.
3. Input signals are changed once during three clock cycles.
4. Input signals are stable.
5. Active standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).
6. Input signals are changed once during tCK(min) .
7. VDD =3.3V
PRELIMINARY July /2001
6
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
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