NT128S64V88C0G-75B 查看數據表（PDF） - Nanya Technology
零件编号
产品描述 (功能)
生产厂家
NT128S64V88C0G-75B Datasheet PDF : 12 Pages
| |||
NT128S64V88C0G
128MB : 16M x 64
Unbuffered SDRAM Module
Read Cycle
Symbol
Parameter
tOH
Data Out Hold Time
tLZ
Data Out to Low Impedance Time
- 7K
- 75B
- 8B
Unit
Min. Max. Min. Max. Min. Max.
-
-
-
-
2.5
-
ns
2.7
-
2.7
-
3
-
ns
0
-
0
-
0
-
ns
tHZ3
Data Out to High Impedance Time
3
5.4
3
5.4
3
6
ns
tDQZ
DQM Data Out Disable Latency
2
-
2
-
2
-
CLK
1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels.
Refresh Cycle
Symbol
Parameter
tREF
tSREX
Refresh Period
Self Refresh Exit Time
- 7K
- 75B
- 8B
Unit
Min. Max. Min. Max. Min. Max.
-
64
-
64
-
64
ms
10
-
10
-
10
-
ns
Write Cycle
Symbol
Parameter
tDS
tDH
tDPL
tDAL3
tDAL2
tDQW
Data In Set-up Time
Data In Hold Time
Data input to Precharge
Data In to Active Delay
CAS Latency = 3
Data In to Active Delay
CAS Latency = 2
DQM Write Mask Latency
- 7K
- 75B
- 8B
Unit
Min. Max. Min. Max. Min. Max.
1.5
-
1.5
-
2
-
ns
0.8
-
0.8
-
1
-
ns
15
-
15
-
15
-
ns
5
-
5
-
5
-
CLK
5
-
-
-
-
-
CLK
0
-
0
-
0
-
ns
Note
1
Note
Note
REV 1.0 07 / 2001
9
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Share Link: 