V436516Y04VATG-75 查看數據表（PDF） - Mosel Vitelic Corporation
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V436516Y04VATG-75 Datasheet PDF : 11 Pages
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MOSEL VITELIC
V436516Y04V
SPD-Table for -75 modules: (Continued)
Byte
Number Function Described
30
Minimum RAS Pulse Width tRAS
31 Module Bank Density (Per Bank)
32 SDRAM Input Setup Time
33 SDRAM Input Hold Time
34 SDRAM Data Input Setup Time
35 SDRAM Data Input Hold Time
36-61 Superset Information (May be used in Future)
62 SPD Revision
63 Checksum for Bytes 0 - 62
64-125 Manufacturers’s Information (Optional)
133 MHz
SPD Entry Value -75PC
42 ns/45 ns
2A
64 MByte
10
1.5 ns/2.0 ns
15
0.8 ns/1.0 ns
08
1.5 ns/2.0 ns
15
0.8 ns/1.0 ns
08
00
Revision 2/1.2
02
D2
00
Hex Value
133 MHZ
-75
2D
10
15
08
15
08
00
02
17
00
100 MHZ
-10PC
2D
10
20
10
20
10
00
12
84
00
126
127
128+
Max. Frequency Specification
Frequency Support Details
Unused Storage Location
133 MHz
Absolute Maximum Ratings
Parameter
Voltage on VDD Supply Relative to VSS
Voltage on Input Relative to VSS
Operating Temperature
Storage Temperature
Power Dissipation
DC Characteristics
TA = 0°C to 70°C; VSS = 0 V; VDD, VDDQ = 3.3V ± 0.3V
Symbol Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
VOH
Output High Voltage (IOUT = –2.0 mA)
VOL
Output Low Voltage (IOUT = 2.0 mA)
II(L)
Input Leakage Current, any input
(0 V < VIN < 3.6 V, all other inputs = 0V)
IO(L)
Output leakage current
(DQ is disabled, 0V < VOUT < VCC)
64
64
64
00
00
00
Max.
-1 to 4.6
-1 to 4.6
0 to +70
-55 to 125
3.5
Units
V
V
°C
°C
W
Limit Values
Min.
Max.
2.0
–0.5
VCC+0.3
0.8
2.4
—
—
0.4
–10
10
–10
10
Unit
V
V
V
V
µA
µA
V436516Y04V Rev. 1.0 October 2001
5
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