V436516Y04V 查看數據表（PDF） - Mosel Vitelic Corporation

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V436516Y04V

128MB 144-PIN UNBUFFERED SDRAM SODIMM, 16MX64 3.3VOLT

Mosel Vitelic Corporation  

MOSEL VITELIC

V436516Y04V

AC Characteristics

TA = 0° to 70°C; VSS = 0V; VCC = 3.3V ± 0.3V, tT = 1 ns (Continued)

# Symbol

Read Cycle

21

tOH

22

tLZ

23

tHZ

24

tDQZ

Write Cycle

25

tWR

26

tDQW

Parameter

Data Out Hold Time

Data Out to Low Impedance Time

Data Out to High Impedance Time

DQM Data Out Disable Latency

Write Recovery Time

DQM Write Mask Latency

-75PC

Min. Max.

2.7

–

1

–

–

5.4

–

2

1

–

0

–

Limit Values

-75

Min. Max.

2.7

–

1

–

–

5.4

–

2

1

–

0

–

-10PC

Min. Max.

2.7

–

1

–

–

5.4

–

2

1

–

0

–

Unit

ns

ns

ns

CLK

CLK

CLK

Note

2

7

Notes:

1. The specified values are valid when addresses are changed no more than once during tCK(min.) and when No

Operation commands are registered on every rising clock edge during tRC(min). Values are shown per module

bank.

2. The specified values are valid when data inputs (DQ’s) are stable during tRC(min.).

3. All AC characteristics are shown for device level.

An initial pause of 100 µs is required after power-up, then a Precharge All Banks command must be given followed

by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can begin.

4. AC timing tests have VIL = 0.4V and VIH = 2.4V with the timing referenced to the 1.4V crossover point. The transition

time is measured between VIH and VIL. All AC measurements assume tT = 1 ns with the AC output load circuit

shown. Specific tac and toh parameters are measured with a 50 pF only, without any resistive termination and with

a input signal of 1V / ns edge rate between 0.8V and 2.0V.

CLOCK

tCL

tSETUP tHOLD

INPUT

1.4V

tCH

2.4V

0.4V

tT

+ 1.4 V

50 Ohm

Z=50 Ohm

I/O

50 pF

OUTPUT

tAC

tLZ

tAC

tOH

tHZ

1.4V

I/O

50 pF

Measurement conditions for

tac and toh

V436516Y04V Rev. 1.0 October 2001

8

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