L6000 查看數據表（PDF） - STMicroelectronics

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L6000

SINGLE CHIP READ & WRITE CHANNEL

STMicroelectronics 

L6000

PIN DESCRIPTION

Pin #

Symbol

Type

POWER SUPPLY

30

Vcc DATA SEP

-

14 Vcc FREQ. SYNTH -

7

Vcc CORE DIG

-

19

Vcc I/O

59 Vcc PULSE DET -

34 GND DATA SEP -

12 GND FREQ SYN -

40 GND CORE DIG -

23

GND I/O

-

5 GND PULSE DET -

INPUT

2, 1

AGC IN,

|

AGC IN

53, 54 DATA PATH,

I

DATA PATH

51, 52 CLOCK PATH,

I

CLOCK PATH

6

PWRDN MODE

I

4 HOLD DATA AGC I

38 HOLD SRV AGC I

47

SERVO REF V

I

37

LATCH CAP A

I

36

LATCH CAP B

I

35 RESET CAP A/B I

60, 61

FILTER IN,

I

FIL TER IN

11 REFERENCE FIN I

22 WRT DATA NRZ I

IN

17

READ GATE

I

26

WRITE CLOCK

I

18

WRITE GATE

I

39

SERVO GATE

I

Description

DATA SEPARATOR: PLL analog 5V supply.

FREQUENCY SYNTHESIZER: PLL analog 5V supply.

Internal ECL, CMOS logic digital supply.

TTL BUFFER I/O 5V SUPPLY.

Pulse Detector/Servo Demodulator/Filter analog 5V supply.

DATA SEPARATOR: PLL analog 5V ground.

FREQUENCY SYNTHESIZERl: PLL analog 5Vground.

Internal ECL, CMOS logic digital ground.

TTL Buffer I/O digital ground.

Pulse Detector/Servo Demodulator/Filter analog circuit ground.

AGC AMPLIFIER INPUTS: Differential AGC amplifier input pins.

ANALOG INPUTS FOR DATA PATH: Differential analog inputs to data

comparators, full-wave rectifier, and servo demodulator.

ANALOG INPUTS FOR CLOCK PATH: Differential analog inputs to the clock

comparator.

PWRDN MODE CONTROL: TTL compatible power control pin. Assertion shuts

down all circuitry, except the serial port. Deassertion and the appropriate bit set

in PD register shuts down the selected circuitry. Active low.

HOLD DATA AGC CONTROL INPUT: TTL compatible power control pin.

Assertion disables the AGC charge pump and holds the input AGC amplifier

gain. Active low.

HOLD DATA AGC CONTROL INPUT: TTL compatible control pin. Assertion

disables the SERVO charge pump. Active low.

SERVO REFERENCE .VOLTAGE INPUT: This voltage is set to half of the Vcc

PULSE DET voltage

LATCH CONTROL INPUT: TTL compatible input. Switches channel A into

peak acquisition mode when low. Cap voltage doesn’t change when high.

LATCH CONTROL INPUT: TTL compatible input. Switches channel B into

peak acquisition mode when low. Cap voltage doesn’t change when high.

RESET CONTROL INPUT: TTL compatible input. Enables the discharge of

channel A & B hold capacitors when asserted. Active low.

FILTER SIGNAL INPUTS: Self biased differential input signals to active filter.

REFERENCE FREQUENCY INPUT: TTL input. Pin REFERENCE FIN has an

internal pull up resistor. In the test mode, when frequency synthesizer is

bypassed, the REFERENCE FIN frequency required is 3 times the data rate.

REFERENCE FIN may be driven by a direct coupled TTL signal.

WRITE DATA NRZ INPUT. TTL input. Connected to the READ NRZ OUTPUT

pin to form a bidirectional data port. Pin WRT DATA NRZ IN has an internal

pull up resistor.

READ GATE : See clocks and Modes.

WRITE CLOCK: TTL input Write mode clock. Must be synchronous with the

Write Data NRZ input. For short cable delays, WRITE CLOCK may be

connected directly to pin READ REF CLOCK. For long cable delays,WRITE

CLOCK should be connected to a READ REF CLOCK return line matched to

the NRZ data bus line delay.

WRITE GATE: TTL input. Enables the write mode. See Clocks and Modes.

SERVO GATE: TTL input. Enables the servo read mode. Active low.

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