VES1993 查看數據表（PDF） - Philips Electronics

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VES1993

Single Chip Satellite Channel Receiver

Philips Electronics 

Philips Semiconductors

Single Chip Satellite Channel Receiver

Product specification

VES1993

FUNCTIONAL DESCRIPTION

½ PLL

The VES 1993 implements a PLL used as clock multiplier by 1, 2, 3, 4 or 6, so that the crystal can be low

frequency.

½ DUAL 6-BIT ADC

The VES 1993 implements a dual 6-bit ADC. The architecture is a standard flash one based on 63 latched

comparators determining simultaneously the precise analog signal level. No external voltage references are

required to use the ADCs.

½ FILTER BANK

The filter bank contains 2 selectable Anti-Alias lowpath filters (AAF) which, combined with cascadable decimation

filters, allows to perform variable rate demodulation capability over a ratio of up to 45.

½ COMPLEX MUTIPLIER

Coherent data demodulation (BPSK or QPSK) is performed by complex multiplication of the incoming symbol

with the computed correction angle. This leads to a rotation and a stabilization of the PSK constellation when the

algorithms of carrier and clock recovery have both converged.

The position of this complex multiplier is programmable and can be either after antialiasing filters or before any

filtering.

½ HALF NYQUIST FILTERS

Half-Nyquist filtering is performed in each arm of the constellation. 2 programmable roll-off are available

depending on the selected standard. The digital filter has 19 (roll-off 0.35) or 25 (roll-off 0.2) taps to provide an

outband attenuation of 40dB.

½ CARRIER SYNCHRONIZER

The carrier synchronizer block implements successively a phase/frequency comparator, a programmable digital

second order loop filter, a phase accumulator (NCO) that accumulates the phase error and drives a sine/cosine

table to determine the angle for correction, applied to the complex multiplier.

½ CLOCK SYNCHRONIZER

The clock phase detector block implements the algorithm for variable rate digital timing recovery. The digital

second order loop filter is programmable, and provides an 8-bit command to the NCO block for clock recovery.

½ AGC

This block calculates the magnitude of the I and Q channels after Nyquist filtering. This value is then compared to

a programmable threshold value, filtered and PWM encoded before being output on the VAGC pin.

½ VITERBI DECODER

The Viterbi decoder performs a maximum likelihood estimation over the received data on the basis of four-bit

quantized samples of the demodulated signals. The average truncation length is 144. The rate R can be chosen

between R = 1/2 and R = 8/9 (punctured codes). Automatic viterbi rate recovery can be selected, so as

automatic spectral inversion ambiguity resolution. The rate search is performed among rates ½, 2/3, ¾, 5/6 and

7/8 In DVB-S standard and among rates 2/3 and 6/7 in DSS mode. Output Bit Error Rate (VBER) is provided by

the decoder. Differential decoding is selectable. The Viterbi decoder provides decoded data and the

corresponding clock.

1999 Jan 01

6

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