L6256 查看數據表（PDF） - STMicroelectronics

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L6256

12V COMBO

STMicroelectronics 

GENERAL BLOCK DESCRIPTIONS

(see figure 1)

Charge Pump

The Charge Pump provides bias for the upper driv-

ers, for the brake circuit, and for internal circuitry as

required for normal and spindown operation. Slew

rate control is built in for quiet operation.

Serial Interface

The serial interface will transfer all control, status

and data to and from the processor. Internal test-

ing provisions have also been made through this

port. The interface is compatible with an

8X196MP,NU or K17 series processor at low

speed only, due to internal limitations of the proc-

essors. External chip select is mandatory on the

L6256. Chip Select is also used to reset and syn-

chronize the serial port. The serial port is used to

indicate thermal shutdown of the Dolphin chip.

Brake Delay Timer

The brake delay will, upon start of a park or brake

sequence, delay 128 negative zero crossings of

the A spindle phase to allow the park circuit to op-

erate. (The delay will typically be on the order of

400 msecs.) Then the braking sequence can be-

gin. The output of this timer is provided to the se-

rial port registers to indicate the start of the brake

action, and to indicate the start and end of the

park period.

3.3V Regulator

The 3.3V external regulator provides a logic 3.3V

using an external pass element (N channel FET),

tied into the undervoltage detection system. It has

the following features:

● Voltage mode control, using no external com-

pensation.

● 3:1 foldback current limit to protect the pass

element in case of component failure.

● Absolute regulation of 8% under all operating

conditions

Control Registers

See serial port section.

Internal Testing

This circuitry is per vendor’s specifications. No

test functions actuated by the serial port software

allow chip or drive damage to inadvertently occur.

Double level write enabling is used. Differing ven-

dor test requirements are accomodated using the

unique vendor code bits. Various external pins

are used for this function; consult the manufac-

turer’s data sheets.

L6256

Spindle Section

SPINDLE CURRENT LIMIT

The spindle current limit value in start mode is set

by the value of the external resistor on the Ref_In

pin during start (which at start is shorted to Vcc,

and the current out of the pin sets the current limit

value).

During run, various internal methods are used to

set a nominal maximum current value for circuit

protection only. Consult the data sheets and ap-

plication notes for a description of this circuitry.

Current limit operates on a cycle by cycle basis.

The current limit comparator output is provided to

the serial port to indicate when the spindle is in

current limit. The current limit bit is reset when

the status register is read.

NOTE: Current limit operation involves chaotic

states, and careful firmware control can be used,

if desired, to prevent audible squels. Actual cur-

rent limit value is also affected significantly by

motor inductance. See application notes.

COMMUTATION COUNTER (CCTR)

The Commutation Counter provides commutation

control for the spindle motor. It advances the

spindle phases according to the bipolar phase

control sequence, every time a SPIN_CLK posi-

tive edge is received. Its reset state (B C\) is gov-

erned by the Commutation Preload Register

(CPR). Operation of the register is synchronous

with SP_CLK, but the reset is asynchronous.

COMMUTATION PRELOAD REGISTER (CPR)

During the initial start period, phase on/off control

is preloaded into the counters from the Commuta-

tion Preload Register, which is loaded from the

serial port. This allows direct commutation con-

trol from the processor. Various commutation

schemes are implemented during startup by soft-

ware through this register. High side bits take

precedence over low side bits.

For both high and low drivers, logic high input to

this register turns on the respective driver. Any

pattern other than all 1’s holds the CCTR in reset,

and sets the MUX to bring data from the CPR

register for the drive pattern. An all 1’s pattern

(an illegal state) releases the CCTR reset and

switches the MUX to read the CCTR.

An all 0 pattern in the CPR spindle control bits

both tristates the spindle drivers and resets the

commutation counter.

The commutation latch holds data from either the

CPR or the CCTR depending on whether all 1’s

are loaded into the CPR. The latch loads the pre-

vious state of the counter when the SP_CLK edge

comes in. The latch circuitry also provides chop

commutation information.

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