LTC1263 查看數據表（PDF） - Linear Technology

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LTC1263

12V, 60mA Flash Memory Programming Supply

Linear Technology 

LTC1263

BLOCK DIAGRAM

VCC

S3A

C1+

S3C

S1

C1

S4A

C1–

S4C

S3B

C2+

C2

C2–

S4B

CLK

S3D

VBGAP BANDGAP

REFERENCE

OSCILLATOR

R1

SHDN

VOUT

R2

VDIV

R3

S2

GND

CIN

COUT

CHARGE PUMP

LTC1263 • BD

S1 AND S2 SHOWN WITH SHDN PIN LOW. S3A, S3B, S3C, S3D, S4A, S4B AND S4C SHOWN CHARGING C1 AND C2

WITH OSCILLATOR OUTPUT LOW AND VDIV < VBGAP – VHYST. AT OSCILLATOR OUTPUT HIGH, S3A, S3B, S3C AND S3D

OPEN WHILE S4A, S4B AND S4C CLOSE TO CHARGE VOUT. COMPARATOR HYSTERESIS IS ±VHYST

TIMING DIAGRAMS

tOFF

VOUT

VSHDN

1.4V

tON

12V

VOUT

5.1V

1.4V

Figure 1. Timing Diagram

VCC

VCC

0V

LTC1263 • F01

4

C1 = 0.47µF

C2 = 0.47µF

1 C1–

SHDN 8

VSHDN

2 C1+

GND 7

LTC1263

3 C2–

VOUT 6

4 C2+

VCC 5

C3 = 10µF

VOUT

C4 = 10µF

VCC

4.75V TO 5.5V

LTC1263 • F02

Figure 2. Timing Circuit

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