XRT71D00IQ(2000) 查看數據表（PDF） - Exar Corporation

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XRT71D00IQ
(Rev.:2000)

E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIZER

Exar Corporation 

XRT71D00

E3/DS3/STS-1 JITTER ATTENUATOR,STS-1 TO DS3 DESYNCHRONIER



REV. 1.01

FIGURE 3. CATEGORY 1 DS3 JITTER TRANSFER MASK

0.1

Acceptable

Range

slope = -20 dB/decade

40

Frequency (Hz)

JITTER TOLERANCE:

The jitter tolerance in the network element is defined

as the maximum amount of jitter in the incoming sig-

nal that it can receive in an “error-free”manner.

JITTER GENERATION:

Jitter generation is defined in Section 7.3.3 of GR-

499-CORE. Jitter generation criteria exists for both

Category I and II interfaces, which consist of “map-

ping” and “pointer adjustment” jitter generation.

Mapping jitter is the sum of the intrinsic payload map-

ping jitter and the jitter that is generated as a result of

the bit stuffing mechnisms used in all of the asynchro-

nous DSn mapping into STS SPE.

JITTER ATTENUATION:

A digital Jitter Attenuation loop combined with the

FIFO provides Jitter attenuation. The Jitter Attenuator

requires no external components except for the refer-

ence clock.

Data is clocked into the FIFO with the associated

clock signal (TClk or RClk) and clocked out of the

FIFO with the dejittered clock and data. When the

FIFO is within 2 bits of being completely full, the FIFO

Limit (FL) will be set.

In Figure 1 and Figure 2, this “de-jittered” clock is la-

beled “Smoothed Clock”. This “Smoothed Clock” is

now used to “Read Out” the “Recovered Data” from

the 16/32 bit FIFO. This “Smoothed Clock” will also

be output to the Terminal Equipment via the “RRClk”

output pin. Likewise, the “Smoothed Recovered Data”

will output to the Terminal Equipment via the RRPOS

and RRNEG output pins.

The XRT71D00 device is designed to work as a com-

panion device with XRT7300 (STS-1/DS3/E3) Line

Interface Unit.

.ETSI TBR24 specifies the maximum output jitter in

loop timing must be no more than 0.4UIpp when mea-

sured between 100Hz to 800KHzwith upto 1.5UI input

jitter at 100Hz.. This means a jitter attenuator with

bandwidth less than 100Hz is required to be compli-

ant with the standard. ITU G.751 is another applica-

tion where low bandwidth jitter attenuator is needed

to smooth the gapped clock output in the de-multi-

plexer system.

SONET STS-1 DS3 MAPPING:

Bellcore GR-253 section 3.4.2 and the ANSI T1.105-

199 describes the asynchronous mapping for DS3 in-

to STS-1 SPE.

11

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