LC72366 查看數據表（PDF） - SANYO -> Panasonic

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LC72366

Single-Chip PLL Microcontrollers

SANYO -> Panasonic 

LC72358N, 72362N, 72366

Electrical Characteristics for the Allowable Operating Ranges

Parameter

Symbol

Conditions

min

typ

max

Unit

Input high level current

IIH (1)

IIH (2)

IIH (3)

XIN: VI = VDD = 5.0 V

FMIN, AMIN, HCTR, LCTR: VI = VDD = 5.0 V

A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD,

HCTR, LCTR, with no pull-down resistor on A port.

VI = VDD = 5.0 V,

with the E, F, G, K, L, M and Q ports selected for input.

2.0

5.0

4.0

10

15 µA

30 µA

3.0 µA

Input low level current

IIH (4)

IIL (1)

IIL (2)

IIL (3)

A port: pull-down resistor present, VI = VDD = 5.0 V

XIN: VI = VSS

FMIN, AMIN, HCTR, LCTR: VI = VSS

A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD,

HCTR, LCTR, with no pull-down resistor on A port.

VI = VSS,

with the E, F, G, K, L, M and Q ports selected for input.

50

2.0

5.0

4.0

10

µA

15 µA

30 µA

3.0 µA

Input floating voltage

VIF

A port: pull-down resistor present

0.05 VDD

V

Pull-down resistance

RPD (1) A port: pull-down resistor present, VDD = 5 V

75

100

200 kΩ

Hysteresis

VH

F, G and K ports, LCTR (period measurement mode)

0.1 VDD

0.2 VDD

V

VOH (1) B and C ports: IO = –1 mA

VDD – 2.0 VDD – 1.0

V

Output high level voltage

VOH (2) D, E, F, G, K, L, M, N, O, P and Q ports: IO = –1 mA

VDD – 1.0

V

VOH (3) EO1, EO2, EO3, SUBPD: IO = –500 µA

VDD – 1.0

V

VOH (4) XOUT: IO = –200 µA

VDD – 1.0

V

VOL (1) B and C ports: IO = 50 µA

1.0

2.0

V

VOL (2) D, E, F, G, K, L, M, N, O, P and Q ports: IO = 1 mA

1.0

V

Output low level voltage

VOL (3) EO1, EO2, EO3, SUBPD: IO = 500 µA

1.0

V

VOL (4) XOUT: IO = 200 µA

1.5

V

VOL (5) J port: IO = 5 mA

2.0

V

IOFF (1) B, C, D, E, F, G, K, L, M, N, O, P and Q ports

–3.0

+3.0 µA

Output off leakage current

IOFF (2) EO1, EO2, EO3, SUBPD

–100

+100 nA

IOFF (3) J port

–5.0

+5.0 µA

A/D conversion error

ADI0 to ADI5: VDD (1)

–1/2

+1/2 LSB

Reject pulse width

PREJ

SNS

50

µs

Power-down detection voltage

VDET

2.7

3.0

3.3

V

Pull-down resistance

RPD (2) TEST1, TEST2

10

kΩ

IDD (1) VDD (1): fIN (2) = 130 MHz, Ta = 25°C

12

24 mA

Current drain

IDD (2)

IDD (3)

VDD (2): Halt mode*, Ta = 25°C (Figure 1)

VDD = 5.5 V, oscillator stopped, Ta = 25°C (Figure 2)

0.45

(0.9) mA

5 µA

IDD (4) VDD = 2.5 V, oscillator stopped, Ta = 25°C (Figure 2)

1 µA

Note: Execute 20 STEP instructions every 1 ms. With the PLL, counters and other functions all stopped.

( ) Value: LC72366

Test Circuit

Note: All of the pins PB to PG and PJ to PQ must be left open.

Here, the pins PE to PG, PK to PM, and PQ are selected for output.

Figure 1: IDD(2) in Halt Mode

Note: All of the pins PA to PQ must be left open.

Figure 2. IDD(3) and IDD(4) in Backup Mode

No. 5065-5/13

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