E
SMART 3 ADVANCED BOOT BLOCK
VCCQ
0.0
INPUT
VCCQ
2
TEST POINTS
VCCQ OUTPUT
2
0580_05
NOTE:
AC test inputs are driven at VCCQ for a logic “1” and 0.0V for a logic “0.” Input timing begins, and output timing ends, at VCCQ/2.
Input rise and fall times (10%–90%) <10 ns. Worst case speed conditions are when VCCQ = VCCQMin.
Figure 5. Input Range and Measurement Points
Device
under
Test
VCCQ
R1
CL
R2
Test Configuration Component Values for Worst
Case Speed Conditions
Test Configuration CL (pF) R1 (Ω) R2 (Ω)
VCCQ1 Standard Test
50
25 K 25 K
VCCQ2 Standard Test
50 16.7 K 16.7 K
NOTE:
Out
CL includes jig capacitance.
NOTE:
See table for component values.
Figure 6. Test Configuration
0580_06
PRELIMINARY
27