LTC1623 查看數據表（PDF） - Linear Technology
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LTC1623 Datasheet PDF : 12 Pages
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LTC1623
U
OPERATIO
Address
The LTC1623 has an address of 1011XXX; the four MSBs
are hard-wired, but the 3 LSBs are programmed by the
user with the help of two three-state address pins. Refer to
Table 1 for the pin configurations and their corresponding
addresses.
To conserve standby current, it is preferable to tie the
address pins to either VCC or GND. If more than four
addresses are needed, then either one of the address pins
can be tied to the third state of VCC/2 by using two equal
value resistors (≤1M) shown in Figure 2. Do not connect
both address pins to the VCC/2 state simultaneously
because this is not a valid address.
Table 1. Address Pin Truth Table
AD0
AD1
ADDRESS
GND
GND
1011000
GND
GND
VCC / 2
VCC / 2
VCC / 2
VCC
VCC
VCC
VCC / 2
VCC
GND
VCC / 2
VCC
GND
VCC / 2
VCC
1011001
1011010
1011011
UNUSED
1011100
1011101
1011110
1011111
1
DATA DATA
CLOCK 2 CLK
8
VCC
7
GA
LTC1623
1M
3
AD0
6
GB
4 GND
AD1 5
1M LOAD1 LOAD2
Charge Pump
To fully enhance the external N-channel switches, an
internal charge pump is used to boost the output gate drive
to a minimum of 2.7V and a maximum of 6V above VCC,
depending on VCC itself. The reason for the maximum
output voltage limit is to avoid switch gate source break-
down due to excessive gate overdrive. A feedback network
is used to limit the charge pump output to 6V above VCC.
Because the output will only need to drive the gate of the
external switch by charging and discharging the parasitic
gate capacitances, the internal charge pump, clocked by
an approximately 300KHz oscillator, is appropriately sized
to source less than 100µA.
Power-On Reset and Undervoltage Lockout
The LTC1623 starts up with both gate drives low. An
internal power-on reset (POR) signal inhibits operation
until about 300µs after VCC crosses the undervoltage
lockout threshold (typically 2V). The circuit includes some
hysteresis and delay to avoid nuisance resets. Once opera-
tion begins, VCC must drop below the threshold for at least
100µs to trigger another POR sequence.
During standby, when both gate drive outputs are dis-
abled, quiescent current is kept to a minimum (13µA
typical) because only the UVLO block is active.
Input Threshold
Anticipating the trend toward lower supply voltages, the
SMBus is specified with a VIH of 1.4V and a VIL of 0.6V.
While some SMBus parts may violate this stringent SMBus
specification by allowing a higher VIH value for a corre-
spondingly higher input supply voltage, the LTC1623
meets and maintains the constant SMBus input threshold
specification across the entire supply voltage range of
2.7V to 5.5V.
1623 F02
Figure 2. LTC1623 Programmed with Address 1011001
8
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