VSC6511RC 查看數據表（PDF） - Vitesse Semiconductor
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VSC6511RC Datasheet PDF : 22 Pages
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VITESSE
SEMICONDUCTOR CORPORATION
SMPTE 292M Serializer, Deserializer, and
Deserializer/Reclocker
Advance Product Information
VSC6511
Deserializer Mode
Features
• Compliant with SMPTE 292M at 1.485Gb/s or 1.485/1.001Gb/s
• Clock and Data Recovery
• 1:20 Deserializer, Descrambler and NRZI Decoder with ENABLE
• Data Framer aligns data to SAV/EAV
• On-chip Clock Multiplier Unit
• CRC Checker
• LINE, FRAME, HANC Indication
• 3.3V, 1300 mW, typical power
• 20 Bit TTL Interface at 74.25MHz or 74.25/1.001MHz
The VSC6511 can be configured as a 20-bit HDTV Deserializer using the MODE[1:0] pins. Serial data from
SDI/SDI is sent to the Clock Recovery Unit (CRU) for clock extraction and data resynchronization. Then the
serial data is descrambled/NRZI decoded, deserialized and synchronously output on D[19:0] by a divided-by-
twenty recovered clock, RCLK. A CRC Checker monitors the output data and indicates any CRC errors on the
CRC pin. Descrambling is enabled by SCREN being HIGH. Data framing aligns the SAV/EAV patterns in the
data with the data bus and RCLK and generates a once-per-line and once-per-frame synchronization output.
D[19:10]
LUMA
CHROMA
D[9:0]
SCREN
Figure 8: Deserializer Mode
SDI
SDI
REFCLK
74.25MHz
Clock
Recovery
Unit
Deserializer
1.485GHz
/20
Clock
Multiply
x20
1.485GHz
NRZI Decoder
Descrambler
CRC Check D Q
Framer
LOCK
CRCERR
LINE
FRAME
HANC
RCLK
Page 10
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52311-0, Rev 2.1
6/25/01
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