VSC6511RC 查看數據表（PDF） - Vitesse Semiconductor

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VSC6511RC

Deserializer/Reclocker SMPTE 292M Serializer, Deserialzer, and

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

SMPTE 292M Serializer, Deserializer, and

Deserializer/Reclocker

Advance Product Information

VSC6511

Clock Recovery Unit

The serial data on the SDI/SDI input is sent to the digital Clock Recovery Unit (CRU) which extracts the

clock and retimes the data. This digital CRU is completely monolithic and requires no external components.

Furthermore, it automatically locks onto data when present and locks to REFCLK when data is not present. This

eliminates the need for the system to control the CRU. The CRU is enabled only in the Deserializer and Deseri-

alizer/Reclocker modes.

Deserializer

The reclocked serial bit stream is deserialized into a 20-bit parallel character. D[0] is serially received prior to

D[1]. The VSC6511 provides a TTL recovered clock, RCLK at one twentieth of the serial bit rate. This clock is

generated by dividing down the high-speed clock from the CRU which is phase locked to the serial data. The

deserializer is enabled only in the Deserializer and Deserializer/Reclocker modes.

If serial input data is not present, or does not meet the required bit rate, the VSC6511 will continue to pro-

duce a recovered clock so that downstream logic may continue to function. The RCLK output frequency under

these circumstances will differ from their expected frequency by less than +1%.

Descrambler and NRZ(I) Decoder

The VSC6511 contains a SMPTE Descrambler/NRZ(I) Decoder which processes the recovered serial data

and outputs unscrambled and NRZ(I) decoded data from the deserializer. The serial scrambled data is descram-

bled/NRZ(I) decoded assuming data has been scrambled/NRZ(I) encoded with the following combined genera-

tor polynomial: G(x)=(x9+x4+1)(x+1). Descrambling is enabled with the SCREN input is HIGH and disabled

when LOW. The descrambler is enabled only in the Deserializer mode.

CRC Checker

The 20-bit data from the Descrambler is sent to the CRC Checker where a running CRC checksum is contin-

uously calculated. As 20-bit data is sent out of the chip, the CRC output pin is asserted if the checksum did not

meet the value expected. This error is asserted from the first CRC Error until the end of the line. A controller

monitors the 20-bit data out of the serializer for SAV/EAV frames in order to control the CRC Checker. The

CRC Checker is enabled only in Deserializer and Deserializer/Reclocker modes.

Framer

The FRAMER block is constructed to generate the following signals: FRAME, LINE, and HANC. These

signals are only provided in Deserializer and Deserializer/Reclocker modes of operation. In Serializer mode,

the outputs will be a constant ‘0’ or LOW.

The LINE and HANC signals are output on a once-per-line basis. The FRAME signal is output on a once-

per-frame basis.

Figure 3 on page 5 provides a more detailed view of the operation of this block.

Page 4

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Internet: www.vitesse.com

G52311-0, Rev 2.1

6/25/01

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